CDK5560 Cirrus Logic Inc, CDK5560 Datasheet - Page 26

• Manufacturer Part Number: CDK5560
• Description: KIT - CDB5560 W/ Capture Plus II System
• Manufacturer: Cirrus Logic Inc
• Series: CapturePLUS™IIr

Specifications of CDK5560

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 50k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±3 V
• Power (typ) @ Conditions: 90mW @ 2.5 V
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 598-1277; CDK5560-1

3.12 Using the CS5560 in Multiplexing Applications
The CS5560 is a delta-sigma A/D converter. Delta-sigma converters use oversampling as means to
achieve high signal to noise. This means that once a conversion is started, the converter takes many sam-
ples to compute the resulting output word. The analog input for the signal to be converted must remain
active during the entire conversion until RDY falls.
The CS5560 can be used in multiplexing applications, but the system timing for changing the multiplexer
channel and for starting a new conversion will depend upon the multiplexer system architecture.
The simplest system is illustrated in
presented to the converter must fully settle. After the signal has settled, the CONV signal is issued to the
converter to start a conversion. Being a delta-sigma converter, the signal must remain present at the input
of the converter until the conversion is completed. Once the conversion is completed, RDY falls. At this
time the multiplexer can be changed to the next channel and the data can be read from the serial port.
The CONV signal should be delayed until after the data is read and until the new analog signal has settled.
In this configuration, the throughput of the converter will be dictated by the settling time of the analog input
circuit and the conversion time of the converter. The conversion data can be read from the serial port after
the multiplexer is changed to the new channel while the analog input signal is settling.
A more complex multiplexing scheme can be used to increase the throughput of the converter is illustrated
in
26
Figure
23. In this circuit, two banks of multiplexers are used.
Advance
CONV
Mux
RDY
CH1+
CH2+
CH3+
CH4+
CH1-
CH2-
CH3-
CH4-
Figure 22. Simple Multiplexing Scheme
Figure
22. Any time the multiplexer is changed, the analog signal
CH1
Settling Time
5/4/09
Amplifier
47pF
47pF
4.99k
4.99k
49.9
49.9
Throughput
4700pF
4700pF
C0G
C0G
Conversion Time
AIN+
AIN-
CH2
CS556x
Settling Time
Amplifier
CS5560
DS713PP2