CDK5560 Cirrus Logic Inc, CDK5560 Datasheet - Page 8

KIT - CDB5560 W/ Capture Plus II System

CDK5560

Manufacturer Part Number
CDK5560
Description
KIT - CDB5560 W/ Capture Plus II System
Manufacturer
Cirrus Logic Inc
Series
CapturePLUS™IIr
Datasheets

Specifications of CDK5560

Number Of Adc's
1
Number Of Bits
24
Sampling Rate (per Second)
50k
Data Interface
Serial
Inputs Per Adc
1 Differential
Input Range
±3 V
Power (typ) @ Conditions
90mW @ 2.5 V
Voltage Supply Source
Dual ±
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
CS5560
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
598-1277
CDK5560-1
SWITCHING CHARACTERISTICS
T
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
8
Serial Port Timing in SSC Mode (SMODE = VL)
Data hold time after SCLK rising
Serial Clock (Out)
(Note 12, 13)
RDY rising after last SCLK rising
CS falling to MSB stable
First SCLK rising after CS falling
CS hold time (low) after SCLK rising
SCLK, SDO tristate after CS rising
SCLK(o)
A
MCLK
= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
SDO
RDY
CS
12. SDO and SCLK will be high impedance when CS is high. In some systems it may require a pull-down resistor.
13. SCLK = MCLK/2.
Figure 2. SSC Mode - Read Timing, CS falling after RDY falls (Not to Scale)
t
11
Parameter
t
12
MSB
MSB–1
Pulse Width (high)
Pulse Width (low)
t
(CONTINUED)
7
5/4/09
t
Symbol
8
t
t
t
t
t
t
t
t
10
12
13
14
11
7
8
9
t
9
Min
50
50
10
-
-
-
-
-
LSB+1
t
13
LSB
Typ
10
10
8
8
5
-
-
-
t
14
t
10
Max
-
-
-
-
-
-
-
-
CS5560
DS713PP2
MCLKs
MCLKs
Unit
ns
ns
ns
ns
ns
ns

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