HSC-ADC-FPGA-9289 Analog Devices Inc, HSC-ADC-FPGA-9289 Datasheet
HSC-ADC-FPGA-9289
Specifications of HSC-ADC-FPGA-9289
Related parts for HSC-ADC-FPGA-9289
HSC-ADC-FPGA-9289 Summary of contents
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... FIFO board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC. The HSC-ADC-FPGA supports up to four/eight ADC channels, providing two parallel CMOS outputs simultaneously. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use ...
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... Theory of Operation ........................................................................ 5 Code Description ......................................................................... 5 Manual Installation and Customization.................................... 5 REVISION HISTORY 10/06—Rev Rev. C Added Quad-/Octal-Channel High Speed Serial LVDS to Parallel CMOS Converter (HSC-ADC-FPGA-8) .....Universal Changes to Figure 2.......................................................................... 4 Changes to Table 1............................................................................ 4 Changes to Figure 3.......................................................................... 5 Changes to Channel Selection Settings Section ........................... 6 Changes to Table 3............................................................................ 6 Changes to Table 4 ...
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... Connect the USB cable to the FIFO evaluation board and to a USB port on the PC. 2. Set the FIFO jumper settings in dual-channel configuration as shown in the HSC-ADC-EVALA/B-DC data sheet, located at www.analog.com/FIFO. 3. Verify and connect the appropriate power supplies to the FIFO, HSDB, and ADC evaluation boards. ...
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... CONNECTOR ADC RESOLUTION DLL RESET JUMPERS Figure 2. HSC-ADC-FPGA-8 Components Comments Requires HSC-ADC-FPGA-9289 and HSC-ADC-EVALA/B-DC (dual-channel) Requires HSC-ADC-FPGA-4/-8 and HSC-ADC-EVALA/B-DC (dual-channel) Requires HSC-ADC-FPGA-4/-8 and HSC-ADC-EVALA/B-DC (dual-channel) Requires HSC-ADC-FPGA-4/-8 and HSC-ADC-EVALA/B-DC (dual-channel) Requires HSC-ADC-FPGA-4/-8 and HSC-ADC-EVALA/B-DC (dual-channel) Requires HSC-ADC-FPGA-4/-8 and HSC-ADC-EVALA/B-DC (dual-channel) Requires HSC-ADC-FPGA-8 and HSC-ADC-EVALA/B-DC (dual-channel) ...
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... Table 4). Once the parallel data has been transferred completely to the FCO clock domain, the data is multiplexed for use with the 2-channel FIFO board (HSC-ADC-EVALA/B-DC). ADC FCO DCO CHA CHB ...
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... HSC-ADC-FPGA JUMPERS RESOLUTION SETTINGS The HSDB supports ADCs with 8 bits to 14 bits of resolution. Use Table 2 to configure the appropriate jumpers. In Table 2, 0 indicates an open jumper, and 1 indicates a shorted jumper. Table 2. Resolution Jumper Settings Number of Bits JP101 CHANNEL SELECTION SETTINGS The ADC Channel A through Channel D are associated with the top IDT FIFO chip, the one closest to the Analog Devices logo ...
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... SPI® INTERFACE The HSDB fully supports ADCs that have an SPI interface. The HSDB does not interact with any of the SPI signals; it provides a path for the SPI interface to be connected from the HSC-ADC- EVALB-DC data capture board to the corresponding product evaluation board. ...
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... EVALUATION BOARD This section describes the optional settings or modes allowed on the HSC-ADC-FPGA-8, Rev. A, HSDB. Note that when using the HSC-ADC-FPGA-8 with a quad ADC, the data is only captured on Channel B of the FIFO4.1 (HSC-ADC- EVALA/B-DC) and displayed on Channel B of the ADC Analyzer software. This is because of the way the first four channels are routed through the PCB and FPGA ...
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... CSB2_CHA 12 C38 C39 SDO_CHA 11 C40 20 VCCJ 3.3V_D 19 VCCO 18 VCCINT 17 TDO TDI_F 16 DNC3 15 DNC4 14 DNC5 13 CEO 12 DNC6 11 GND Figure 6. PCB Schematic Rev Page HSC-ADC-FPGA PARALLEL CMDS OUTPUTS TO FIFO BOARD J200 J200 B1 A1 D1_17 B2 A2 D1_16 B10 A10 B11 A11 B12 A12 B13 ...
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... HSC-ADC-FPGA SERIAL LVDS INPUTS FROM EVAL BOARD U100: A DCO B8 IO_L96N_0 R100 A8 100Ω IO_L96P_0 DCO FCO D8 IO_L95N_0 R101 C8 100Ω IO_L95P_0 FCO CHA CHA E1 IO_L04P_7 R102 E2 100Ω IO_L04N_7 CHA CHB F3 IO_L43P_7 R103 F4 100Ω IO_L43N_7 CHB CHC G1 IO_L93P_7 R104 G2 100Ω ...
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... C325 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF C332 C333 C334 C335 C336 1nF 1nF 1nF 1nF 1nF Figure 8. PCB Schematic (Continued) Rev Page HSC-ADC-FPGA L303 10µH 2 OUT 3.3V 4 C304 OUT 1µ MOUNTING HOLES CONNECTED TO GROUND C326 C327 0.1µ ...
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... HSC-ADC-FPGA Figure 9. Layer 1—Primary Side (Top) Rev Page ...
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... Figure 10. Layer 2—Ground Plane Rev Page HSC-ADC-FPGA ...
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... HSC-ADC-FPGA Figure 11. Layer 3—+1.5 V Power Plane and Signal Rev Page ...
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... Figure 12. Layer 4—+3.3V Power Plane and Signal Rev Page HSC-ADC-FPGA ...
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... HSC-ADC-FPGA Figure 13. Layer 5—Ground Plane Rev Page ...
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... Figure 14. Layer 6—Secondary Side (Bottom) Rev Page HSC-ADC-FPGA ...
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... HSC-ADC-FPGA ORDERING INFORMATION BILL OF MATERIALS 1 Table 6. Component Listing Item Qty REFDES 1 1 HSC-ADC-FPGA-8-EBZ 2 15 C309, C310, C311, C312, C317, C318, C319, C320, C321, C322, C323, C324, C325, C326, C327 3 2 C305, C307 4 2 C306, C308 5 15 C313, C314, C315, C316, C328, ...
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... XC2V250-5FG256C-2020, FPGA IC SSOT XCF02SV020C, EPROM Part of CBSB-14-01A-RT, assembly 7/8" height, standoffs for circuit board support Part of SNT-100-BK-G-H, assembly 100 mil jumpers Rev Page HSC-ADC-FPGA Manufacturer and Part No. Analog Devices, ADP3339AKC-3.3-RL Analog Devices, ADP3339AKC-1.5-RL Xilinx, XC2V250-5FG256C Xilinx, XCF02SV020C Richco, CBSB-14-01A-RT Samtec, SNT-100-BK-G-H ...
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... HSC-ADC-FPGA ORDERING GUIDE Model Package Description HSC-ADC-FPGA-9289 Quad-Channel High Speed Serial LVDS to Parallel CMOS Converter for the AD9289 only HSC-ADC-FPGA-4 Quad-Channel High Speed Serial LVDS to Parallel CMOS Converter for the AD9287, AD9219, AD9228, AD9229, AD9259 HSC-ADC-FPGA-8 Quad-/Octal-Channel High Speed Serial LVDS to Parallel CMOS Converter for the AD9287, AD9219, AD9228, ...