HSC-ADC-FPGA-9289 Analog Devices Inc, HSC-ADC-FPGA-9289 Datasheet - Page 8

• Manufacturer Part Number: HSC-ADC-FPGA-9289
• Description: EVAL BOARD FPGA FOR AD9289
• Manufacturer: Analog Devices Inc

Specifications of HSC-ADC-FPGA-9289

• Accessory Type: ADC Interface Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: AD9289 (Requires HSC-ADC-EVAL-DC)

HSC-ADC-FPGA
EVALUATION BOARD
This section describes the optional settings or modes allowed
on the HSC-ADC-FPGA-8, Rev. A, HSDB. Note that when
using the HSC-ADC-FPGA-8 with a quad ADC, the data is
only captured on Channel B of the FIFO4.1 (HSC-ADC-
EVALA/B-DC) and displayed on Channel B of the ADC
Analyzer software. This is because of the way the first four
channels are routed through the PCB and FPGA.
The HSDB provides all of the support circuitry required to
accept quad/octal ADC digital serial LVDS outputs. Each of the
various functions and configurations can be selected by proper
connection of various jumpers (see Figure 6 to Figure 8). When
using this in conjunction with an ADC evaluation board and
FIFO, it is critical that the signal sources used for the analog
input and clock have very low phase noise (<1 ps rms jitter) to
realize the ultimate performance of the converter. Proper
filtering of the analog input signal to remove harmonics and
lower the integrated or broadband noise at the input is also
necessary to achieve the specified noise performance.
See Figure 6 to Figure 8 for complete schematics and
layout plots.
WALL OUTLET
100-240VAC
47-63Hz
ROHDE & SCHWARZ,
ROHDE & SCHWARZ,
2V p-p SIGNAL
2V p-p SIGNAL
SYNTHESIZER
SYNTHESIZER
SMHU,
SMHU,
Figure 5. Example Setup Using Quad/Octal ADC Evaluation Board and FIFO Data Capture Board
SWITCHING
SUPPLY
POWER
BAND-PASS
FILTER
XFMR
INPUT
CLK
EVALUATION
BOARD
CHA–CHD
CHE–CHH
OUTPUTS
SERIAL
LVDS
SPI
OR
Rev. C | Page 8 of 20
2Amax
6VDC
DESERIALIZATION
HSC-ADC-FPGA
–
HIGH SPEED
3.3V
8-BIT TO 14-BIT
BOARD
POWER SUPPLIES
The HSDB board is supplied with a wall mount switching
power supply that provides a 6 V, 2 A maximum output.
Connect the supply to the rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter
jack that connects to the PCB at J300. On the PC board, the 6 V
supply is then fused and conditioned before connecting to two
low dropout linear regulators that supply the proper bias to each
of the various sections on the board (see Figure 5).
When operating the evaluation board in a nondefault condition,
L302 and L303 can be removed to disconnect the switching
power supply. This enables the user to bias each section of the
board individually. Use P301 to connect a different supply for
each section. The 3.3 V supply with a 1 A current capability is
needed to bias the input/output supply ring pins of the FPGA.
In addition to the 3.3 V supply, the 1.5 V supply is needed with
a 1 A current capability to bias the core supply pins of the FPGA.
+
SPI
PARALLEL
–
1.5V
CMOS
2 CH
+
HSC-ADC-EVALB-DC
FIFO DATA
CAPTURE
BOARD
SPI
CONNECTION
USB
ANALYZER
SPI
RUNNING
ADC
PC