HSC-ADC-FPGA-9289 Analog Devices Inc, HSC-ADC-FPGA-9289 Datasheet - Page 6

• Manufacturer Part Number: HSC-ADC-FPGA-9289
• Description: EVAL BOARD FPGA FOR AD9289
• Manufacturer: Analog Devices Inc

Specifications of HSC-ADC-FPGA-9289

• Accessory Type: ADC Interface Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: AD9289 (Requires HSC-ADC-EVAL-DC)

HSC-ADC-FPGA
JUMPERS
RESOLUTION SETTINGS
The HSDB supports ADCs with 8 bits to 14 bits of resolution.
Use Table 2 to configure the appropriate jumpers. In Table 2,
0 indicates an open jumper, and 1 indicates a shorted jumper.
Table 2. Resolution Jumper Settings
Number of Bits
8
10
12
14
CHANNEL SELECTION SETTINGS
The ADC Channel A through Channel D are associated with
the top IDT FIFO chip, the one closest to the Analog Devices
logo; Channel B; or ADC Analyzer Channel B. ADC Channel E
through Channel H are associated with the bottom IDT FIFO
chip, Channel A, or ADC Analyzer Channel A. Use Table 3 to
configure the jumper settings for channel selection. In Table 3,
0 indicates an open jumper, and 1 indicates a shorted jumper.
Table 3. Channel Selection Jumper Settings
ADC Channel
A
B
C
D
E
F
G
H
DATA ALIGNMENT
The DLL/Timing Reset button (PB101) must be pressed to
operate the HSDB after initial power-up. Data alignment is
automatic; however, the DLL/Timing Reset button must be
pressed any time the ADC sample clock rate is changed, or data
outputs become corrupted.
After pressing the DLL/Timing Reset button, the FPGA digital
clock manager (DCM) DLL is reset to its default setting. This
value (PHASE_SHIFT) is defined in the user constraints file of
the FPGA software and is shown in Table 4.
Table 4. Default PHASE_SHIFT User Constraint Settings
Product
AD9289
AD9229
AD9219/AD9228/
AD9259/AD9287
AD9212/AD9222/
AD9252
FIFO Channel/
ADC Analyzer Channel
Channel B/Channel B
Channel B/Channel B
Channel B/Channel B
Channel B/Channel B
Channel A/Channel A
Channel A/Channel A
Channel A/Channel A
Channel A/Channel A
JP101
0
0
1
1
PHASE_SHIFT User Constraint
+50
−10
−10
−10
Channel Select
JP103 = 0, JP104 = 0
JP103 = 0, JP104 = 1
JP103 = 1, JP104 = 0
JP103 = 1, JP104 = 1
JP105 = 0, JP106 = 0
JP105 = 0, JP106 = 1
JP105 = 1, JP106 = 0
JP105 = 1, JP106 = 1
JP102
0
1
0
1
Rev. C | Page 6 of 20
DCO PHASE ALIGNMENT
The DCO Phase Shift button (PB100) can be used in
conjunction with the DCO Phase Shift jumper (JP100) to adjust
the phase relationship between the incoming DCO signal and
the FPGA DLL signal.
The output of the FPGA DLL is used to capture the incoming
serial data streams. The rising edge and falling edge of this
signal must be aligned, so that they occur during the center of
the data eye as shown in Figure 4.
After activating the DLL/Timing Reset button (PB101), the
phase of the DLL is set to its default value. If this phase
alignment setting is not compatible with the current
configuration of the ADC under test, it can be adjusted.
The phase shift operation is activated by pressing the DLL
Phase Shift button (PB100). The direction of this adjustment is
determined by the setting of the DLL Phase Shift jumper
(JP100); see Table 5.
Table 5. DCO Phase Shift Alignment Settings
DCO Phase Shift
Increment
Decrement
While the DLL Phase Shift button is clicked, the phase is
adjusted continuously over the range of the PHASE_SHIFT
user constraint. The PHASE_SHIFT variable can be set to any
integer value between ±255. The actual setting of this variable is
lost when using this function. However, an out-of-range condition
is indicated by LED CR100. If the phase has gone out of range,
it can be set back in range either by using the DLL/Timing Reset
button (PB101) or by changing the adjustment direction using
Jumper JP100 and clicking the PB100 button again.
The rate of phase change while the PB100 button is clicked
is determined by multiplying the FCO clock period by
2
that it takes to slew from PHASE_SHIFT = 0 to the minimum
or maximum value. For example, if FCO = 65 MHz, it takes
approximately 2 sec to slew from PHASE_SHIFT = 0 to out-of-
range (2
further details on DCM phase shifting.
27
(256 steps × 2
27
FPGA DLL–
FPGA DLL+
× 1/65M). Refer to the Xilinx Virtex-II data sheet for
Figure 4. DCO Phase Shifting Alignment Example
DCO–
DCO+
D–
D+
19
). This gives the amount of time in seconds
JP100
0
1
t
0
MSB
t
DATA
MSB – 1
MSB – 2