HSC-ADC-FPGA-9289 Analog Devices Inc, HSC-ADC-FPGA-9289 Datasheet - Page 7

• Manufacturer Part Number: HSC-ADC-FPGA-9289
• Description: EVAL BOARD FPGA FOR AD9289
• Manufacturer: Analog Devices Inc

Specifications of HSC-ADC-FPGA-9289

• Accessory Type: ADC Interface Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: AD9289 (Requires HSC-ADC-EVAL-DC)

SPI® INTERFACE
The HSDB fully supports ADCs that have an SPI interface. The
HSDB does not interact with any of the SPI signals; it provides a
path for the SPI interface to be connected from the HSC-ADC-
EVALB-DC data capture board to the corresponding product
evaluation board.
FIFO JUMPER SETTINGS
The HSDB requires the interface of the HSC-ADC-EVALA/B-
DC (dual-channel FIFO4 or FIFO4.1) for data to be captured
and displayed in the ADC Analyzer. The default settings for
the FIFO dual-channel configuration can be found in the
HSC-ADC-EVALA/B-DC data sheet at www.analog.com/FIFO.
To align the timing properly, some evaluation boards require
modifications to these settings. For proper operation, the FIFO
timing setting should be configured for dual-channel config-
uration. For more details, see the Theory of Operation section
in the HSC-ADC-EVALA/B-SC/HSC-ADC-EVALA/B-DC data
sheet at www.analog.com/FIFO.
Rev. C | Page 7 of 20
Another easy way to determine if the proper jumper settings
between the HSDB, FIFO, and ADC Analyzer have already
been installed is to consult the help menu in the ADC Analyzer
software:
1.
2.
3.
From the Help menu, select About HSC_ADC_EVALA.
Click Setup Default Jumper Wizard.
Click Dual Channel. A picture of the FIFO board for that
application appears, showing the correct jumper settings
already in place.
HSC-ADC-FPGA