AD5522JSVUZ Analog Devices Inc, AD5522JSVUZ Datasheet - Page 37

• Manufacturer Part Number: AD5522JSVUZ
• Description: Quad PPMU With DACs And LVDS/SPI
• Manufacturer: Analog Devices Inc

Specifications of AD5522JSVUZ

• Design Resources: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The calibration engine is engaged only when data is written to
the X1 register and for some PMU writes (see Table 18). The
calibration engine is not engaged when data is written to the M
or C register. This has the advantage of minimizing the initial
setup time of the device. To calculate a result that includes new
M or C data, a write to X1 is required.
CACHED X2 REGISTERS
Each DAC has a number of cached X2 registers. These registers
store the result of a gain and offset calibration in advance of a mode
change. This enables the user to preload registers, allowing the
calibration engine to calculate the appropriate X2 value and store
it until a change in mode occurs. Because the data is ready and
held in the appropriate register, mode changing is as time efficient
as possible. If an update occurs to a DAC register set that is
currently part of the operating PMU mode, the DAC output is
updated immediately (depending on the LOAD condition).
Gain and Offset Registers for the FIN DAC
The force amplifier input (FIN) DAC level contains independent
gain and offset control registers that allow the user to digitally
trim gain and offset. There are six sets of X1, M, and C registers:
one set for the force voltage range and one set for each force
current range (four internal current ranges and one external
current range). Six X2 registers store the calculated DAC values,
ready to load to the DAC register upon a PMU mode change.
Gain and Offset Registers for the Comparator DACs
The comparator DAC levels contain independent gain and
offset control registers that allow the user to digitally trim gain
and offset. There are six sets of X1, M, and C registers: one set
for the force voltage mode and one set for each force current
range (four internal current ranges and one external current
range). In this way, X2 can be preprogrammed, which allows for
efficient switching into the required compare mode. Six X2
registers store the calculated DAC values, ready to load to the
DAC register upon a PMU mode change.
SERIAL I/F
VREF
SERIAL I/F
16
16
16
16
16
16
16
16
16
X1 REG
M REG
C REG
X1 REG
X1 REG
M REG
M REG
Figure 52. Comparator Registers
C REG
C REG
Figure 51. FIN DAC Registers
×6
×6
×6
X2 REG
OFFSET DAC
X2 REG
X2 REG
16
VREF
FIN DAC
16-BIT
16
16
CPH DAC
CPL DAC
16-BIT
16-BIT
CPH
CPL
FIN
Rev. D | Page 37 of 64
Gain and Offset Registers for the Clamp DACs
The clamp DAC levels contain independent gain and offset
control registers that allow the user to digitally trim gain and
offset. There are two sets of X1, M, and C registers: one set for
the force voltage mode and one set for all five current ranges.
Two X2 registers store the calculated DAC values, ready to load
to the DAC register upon a PMU mode change.
REFERENCE VOLTAGE (VREF)
One buffered analog input, VREF, supplies all 21 DACs with the
necessary reference voltage to generate the required dc levels.
REFERENCE SELECTION
The voltage applied to the VREF pin determines the output
voltage range and span applied to the force amplifier, clamp, and
comparator inputs. The AD5522 can be used with a reference
input ranging from 2 V to 5 V; however, for most applications,
a reference input of 5 V or 2.5 V is sufficient to meet all voltage
range requirements. The DAC amplifier gain is 4.5, which gives
a DAC output span of 22.5 V. The DACs have gain and offset
registers that can be used to trim out system errors.
In addition, the gain register can be used to reduce the DAC
output range to the desired force voltage range. The FIN DAC
retains 16-bit resolution even with a gain register setting of
quarter scale (0x4000). Therefore, from a single 5 V reference,
it is possible to obtain a voltage span as high as 22.5 V or as low
as 5.625 V.
When using the gain and offset registers, the selected output
range should take into account the system gain and offset errors
that need to be trimmed out. Therefore, the selected output
range should be larger than the actual required range.
When using low supply voltages, ensure that there is sufficient
headroom and footroom for the required force voltage range.
Also, the forced current range is the quoted full-scale range only
with an applied reference of 5 V (I
2.5 V (I
VREF
SENSE
SERIAL I/F
amplifier gain = 5).
16
16
16
16
16
16
X1 REG
X1 REG
Figure 53. Clamp Registers
M REG
C REG
M REG
C REG
×2
×2
SENSE
X2 REG
X2 REG
amplifier gain = 10) or
16
16
CLH DAC
CLL DAC
16-BIT
16-BIT
AD5522
CLH
CLL