AD5522JSVUZ Analog Devices Inc, AD5522JSVUZ Datasheet - Page 44

• Manufacturer Part Number: AD5522JSVUZ
• Description: Quad PPMU With DACs And LVDS/SPI
• Manufacturer: Analog Devices Inc

Specifications of AD5522JSVUZ

• Design Resources: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5522
REGISTER UPDATE RATES
The value of the X2 register is calculated each time the user writes
new data to the corresponding X1 register and for some PMU
register updates. The calculation is performed in a three-stage
process. The first two stages take approximately 650 ns each, and
the third stage takes approximately 350 ns. When the write to the X1
register is complete, the calculation process begins. If the write
operation involves the update of a single DAC channel, the user is
free to write to another X1 register, provided that the write
operation does not finish ( SYNC returns high) until after the
first-stage calculation is complete, that is, 650 ns after the
completion of the first write operation.
REGISTER SELECTION
The serial word assignment consists of 29 bits. Bit 28 to Bit 22
are common to all registers, whether writing to or reading from
the device. The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address
each PMU channel (or associated DAC register). When the
PMU3 to PMU0 bits are all 0s, the system control register is
addressed.
The mode bits, MODE0 and MODE1, address the different sets
of DAC registers and the PMU register.
Figure 57. Multiple Single-Channel Writes Engaging the Calibration Engine
WRITE 1
~650ns
WRITE 2
STAGE
FIRST
650ns
CALIBRATION ENGINE TIME
SECOND
WRITE 3
STAGE
STAGE
650ns
FIRST
SECOND
STAGE
STAGE
STAGE
THIRD
350ns
FIRST
SECOND
STAGE
STAGE
THIRD
STAGE
THIRD
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Table 19. Mode Bits
B23
MODE1
0
0
1
1
Readback Control, RD/ WR
Setting the RD/ WR bit (Bit 28) high initiates a readback
sequence of the PMU, alarm status, comparator status, system
control, or DAC register, as determined by the address bits.
PMU Address Bits: PMU3, PMU2, PMU1, PMU0
The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address each
PMU channel on chip. These bits allow individual control of
each PMU channel or any combination of channels, in addition
to multichannel programming. PMU bits also allow access to
write registers such as the system control register and the DAC
registers, in addition to reading from all the registers (see Table 20).
NOP (No Operation)
If an NOP (no operation) command is loaded, no change is
made to the DAC or PMU registers. This code is useful when
performing a readback of a register within the device (via the
SDO pin) where a change of DAC code or PMU function may
not be required.
Reserved Commands
Any bit combination that is not described in the register address
tables for the PMU, DAC, and system control registers indicates
a reserved command. These commands are unassigned and are
reserved for factory use. To ensure correct operation of the
device, do not use reserved commands.
B22
MODE0
0
1
0
1
Action
Write to the system control register or
the PMU register
Write to the DAC gain (M) register
Write to the DAC offset (C) register
Write to the DAC input data (X1) register