AD5522JSVUZ Analog Devices Inc, AD5522JSVUZ Datasheet - Page 43

• Manufacturer Part Number: AD5522JSVUZ
• Description: Quad PPMU With DACs And LVDS/SPI
• Manufacturer: Analog Devices Inc

Specifications of AD5522JSVUZ

• Design Resources: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Because there is only one calibration engine shared among four
channels, the task of calculating X2 values must be done sequentially,
so that the length of the BUSY pulse varies according to the
number of channels being updated. Following any register
update, including multiple channel updates, subsequent writes
should either be timed or should wait until BUSY returns high
(see Figure 56). If subsequent writes are presented before the
calibration engine completes the first stage of the last Channel X2
calculation, data may be lost.
Table 17.
Action
Loading Data to System Control
Loading X1 to 1 PMU DAC Channel
Loading X1 to 2 PMU DAC Channels
Loading X1 to 3 PMU DAC Channels
Loading X1 to 4 PMU DAC Channels
1
2
Table 18.
Bit
21
20, 19
17, 16, 15
14, 13
12
11
10
9
8
7
6
BUSY pulse width = ((number of channels + 1) × 650 ns) + 350 ns.
Refer to Table 18 for details of PMU register effect on BUSY pulse width.
Register, or Readback
BUSY
A A
BUSY
A A
Bit Name
CH EN
FORCE1, FORCE0 (depends on mode change)
Transition From
High-Z FOHx current (11)
High-Z FOHx current (11)
High-Z FOHx current (11)
Force current (01)
Force current (01)
Force current (01)
High-Z FOHx voltage (10)
High-Z FOHx voltage (10)
High-Z FOHx voltage (10)
Force voltage (00)
Force voltage (00)
Force voltage (00)
C2 to C0; current range selection (any range change)
MEASx (measure mode selection)
FIN
SFO
SS0
CL
CPOLH
Compare V/I
Clear
E E
A A
E E
A A
Pulse Widths
Pulse Widths for PMU Register Updates
2
PMU Register Update (See
BUSY Pulse Width
0.27 μs maximum
1.65 μs maximum
2.3 μs maximum
2.95 μs maximum
3.6 μs maximum
Transition To
Force current (01)
Force voltage (00)
High-Z FOHx voltage (10)
High-Z FOHx current (11)
High-Z FOHx voltage (10)
Force voltage (00)
Force voltage (00)
Force current (01)
High-Z FOHx current (11)
High-Z FOHx voltage (10)
High-Z FOHx current (11)
Force current (01)
Table 26
Rev. D | Page 43 of 64
1
)
BUSY also goes low during a power-on reset and when a falling
edge is detected on the RESET pin.
Writing data to the system control register, some PMU control
bits (see Table 18), the M register, and the C register do not
involve the digital calibration engine, thus speeding up
configuration of the device on power-on. However, care should
be taken not to issue these commands while BUSY is low, as
previously described.
WRITE 1
~650ns
STAGE
650ns
FIRST
CALIBRATION ENGINE TIME
Figure 56. Multiple Writes to DAC X1 Registers
One
Channel
1.65 μs
1.65 μs
1.65 μs
1.65 μs
1.65 μs
1.65 μs
1.65 μs
1.65 μs
1.65 μs
1.65 μs
Maximum BUSY Low Time per Channel Update
SECOND
STAGE
STAGE
650ns
FIRST
SECOND
WRITE 2
Two
Channels
2.3 μs
2.3 us
2.3 μs
2.3 μs
2.3 μs
2.3 μs
2.3 μs
2.3 μs
2.3 μs
2.3 μs
STAGE
STAGE
STAGE
THIRD
FIRST
350ns
SECOND
STAGE
STAGE
STAGE
270 ns
270 ns
270 ns
270 ns
270 ns
270 ns
270 ns
270 ns
270 ns
270 ns
270 ns
270 ns
THIRD
FIRST
Three
Channels
2.95 μs
2.95 us
2.95 μs
2.95 μs
2.95 μs
2.95 μs
2.95 μs
2.95 μs
2.95 μs
2.95 μs
SECOND
STAGE
STAGE
THIRD
AD5522
FOR EXAMPLE,
WRITE TO 3 FIN
DAC REGISTERS
Four
Channels
3.6 μs
3.6 μs
3.6 μs
3.6 μs
3.6 μs
3.6 μs
3.6 μs
3.6 μs
3.6 μs
3.6 μs
STAGE
THIRD