AD5522JSVUZ Analog Devices Inc, AD5522JSVUZ Datasheet - Page 48

• Manufacturer Part Number: AD5522JSVUZ
• Description: Quad PPMU With DACs And LVDS/SPI
• Manufacturer: Analog Devices Inc

Specifications of AD5522JSVUZ

• Design Resources: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5522
WRITE PMU REGISTER
To address PMU functions, set the MODE1 and MODE0 bits
to 0. This setting selects the PMU register (see Table 19 and
Table 20). The AD5522 has very flexible addressing, which
allows writing of data to a single PMU channel, any
Table 24. PMU Register Bits—Bit B28 to Bit B15
B28
RD/WR
1
Table 25. PMU Register Bits—Bit B14 to Bit B0
B14
MEAS1
1
Table 26. PMU Register Functions
Bit
28 (MSB)
27
26
25
24
23
22
PMU Register-Specific Bits
21
20
19
18
17
16
15
Bit B18 is reserved.
Bit B5 to Bit B0 are unused data bits.
B27
PMU3
B13
MEAS0
Bit Name
RD/WR
PMU3
PMU2
PMU1
PMU0
MODE1
MODE0
CH EN
FORCE1
FORCE0
Reserved
C2
C1
C0
B12
FIN
B26
PMU2
Description
When low, a write to the selected register takes place; setting the RD/WR bit high initiates a readback sequence
of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the address bits.
Bit PMU3 to Bit PMU0 address each PMU channel in the device. These bits allow control of an individual PMU
channel or any combination of channels, in addition to multichannel programming (see Table 20).
Set the MODE1 and MODE0 bits to 0 to access the PMU register selected by the PMU3 to PMU0 bits (Bit 27 to
Bit 24).
Channel enable. Set high to enable the selected channel or group of channels; set low to disable the selected
channel or channels. When disabled, SW2 is closed and SW5 is open (outputs are high-Z). The measure mode is
determined by the MEAS1 and MEAS0 bits at all times and is not affected by the CH EN bit. The guard amplifier
and the comparators are not affected by this bit.
The FORCE1 and FORCE0 bits set the force function for each PMU channel (in association with the PMUx bits).
All combinations of forcing and measuring (using the MEAS1 and MEAS0 bits) are available. The high-Z (voltage
and current) modes allow the user to optimize glitch response during mode changes. While in high-Z voltage or
current mode, with the PMU high-Z, new X1 codes loaded to the FIN DAC register and to the clamp DAC register
are calibrated, stored in the X2 register, and loaded directly to the DAC outputs.
FORCE1
0
0
1
1
0
Bit C2 to Bit C0 specify the required current range. High-Z FV/FI commands ignore the current range address
bits (C2, C1, and C0); therefore, these bit combinations cannot be used to enable or disable the force function
for a PMU channel.
C2
0
0
0
0
1
1
1
1
B25
PMU1
B11
SF0
C1
0
0
1
1
0
0
1
1
B10
SS0
B24
PMU0
FORCE0
0
1
0
1
B9
CL
B23
MODE1
C0
0
1
0
1
0
1
0
1
Rev. D | Page 48 of 64
B22
MODE0
B8
CPOLH
FI and voltage clamp (if clamp is enabled).
±external current range.
Enable the always on mode for the external current range buffer
Reserved.
Action
FV and current clamp (if clamp is enabled).
High-Z FOHx voltage (preload FIN DAC and clamp DAC).
High-Z FOHx current (preload FIN DAC and clamp DAC).
Selected Current Range
±5 μA current range.
±20 μA current range.
±200 μA current range.
±2 mA current range (default).
Disable the always on mode for the external current range buffer
B7
Compare V/I
B21
CH EN
combination of PMU channels, or all PMU channels. This
functionality enables multipin broadcasting to similar pins on
a DUT. Bit 27 to Bit 24 select the PMU or group of PMUs that
is addressed.
B20
FORCE1
B6
Clear
B19
FORCE0
B5
0
1
B4
0
1
B18
0
1
B3
0
1
B17
C2
B2
0
1
B16
C1
B1
0
2
1
.
.
1
B15
C0
B0
0
1