AD8197ASTZ-RL Analog Devices Inc, AD8197ASTZ-RL Datasheet
AD8197ASTZ-RL
Specifications of AD8197ASTZ-RL
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AD8197ASTZ-RL Summary of contents
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FEATURES 4 inputs, 1 output HDMI™/DVI links Enables HDMI 1.3-compliant receiver Pin-to-pin compatible with the AD8191 4 TMDS® channels per link Supports 250 Mbps to 2.25 Gbps data rates Supports 25 MHz to 225 MHz pixel clocks Equalized inputs for ...
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AD8197 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Typical Application........................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Maximum ...
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SPECIFICATIONS T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input A swing = 1000 mV, TMDS ...
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AD8197 Parameter 5 SERIAL CONTROL INTERFACE Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage PARALLEL CONTROL INTERFACE Input High Voltage Input Low Voltage ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter AVCC to AVEE DVCC to DVEE DVEE to AVEE VTTI VTTO AMUXVCC Internal Power Dissipation High Speed Input Voltage High Speed Differential Input Voltage Low Speed Input Voltage and Parallel Logic ...
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AD8197 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AVCC 1 PIN 1 INDICATOR IN_B0 2 IP_B0 3 AVEE 4 IN_B1 5 IP_B1 6 VTTI 7 IN_B2 8 IP_B2 9 AVEE 10 IN_B3 11 IP_B3 12 AVCC 13 IN_A0 14 IP_A0 15 AVEE ...
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Pin No. Mnemonic 24 IP_A3 26 I2C_ADDR0 27 I2C_ADDR1 28 I2C_ADDR2 29, 95 DVEE 30 PP_CH0 31 PP_CH1 32, 38, 47 DVCC 33 ON0 34 OP0 35, 41 VTTO 36 ON1 37 OP1 39 ON2 40 OP2 42 ON3 43 ...
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AD8197 Pin No. Mnemonic 90 AUX_COM0 91 AUX_B3 92 AUX_B2 93 AUX_B1 94 AUX_B0 96 AUX_A3 97 AUX_A2 98 AUX_A1 99 AUX_A0 100 PP_OTO high speed low speed input output. 1 ...
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TYPICAL PERFORMANCE CHARACTERISTICS T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input A swing = 1000 ...
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AD8197 T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input A swing = 1000 mV, TMDS ...
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T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input A swing = 1000 mV, TMDS outputs ...
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AD8197 T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input A swing = 1000 mV, TMDS ...
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THEORY OF OPERATION INTRODUCTION The AD8197 is a pin-to-pin HDMI 1.3 receive-compliant replacement for the AD8191. The primary function of the AD8197 is to switch one of four (HDMI or DVI) single-link sources to one output. Each HDMI/DVI link consists ...
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AD8197 VTTO 50Ω 50Ω OPx DISABLE I OUT AVEE Figure 26. High Speed Output Simplified Schematic The AD8197 requires output termination resistors when the high speed outputs are enabled. Termination can be internal and/or external. The internal terminations of the ...
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This precaution does not need to be taken if the DDC peripheral circuitry is connected to the bus downstream of the AD8197. +5V INTERNAL (IF ANY) PIN 18 HDMI CONNECTOR PIN 18 HDMI CONNECTOR PIN 14 DVI CONNECTOR PIN 14 ...
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AD8197 SERIAL CONTROL INTERFACE RESET On initial power-up any point in operation, the AD8197 register set can be restored to preprogrammed default values by pulling the RESET pin to low in accordance with the specifica- tions in Table ...
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I2C_SCL GENERAL CASE FIXED PART START ADDR I2C_SDA ADDR EXAMPLE I2C_SDA 1 2 READ PROCEDURE To read data from the AD8197 register set microcontroller) needs to send the appropriate control signals to the AD8197 slave device. ...
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AD8197 PARALLEL CONTROL INTERFACE The AD8197 can be controlled through the parallel interface using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and PP_OCL pins. Logic levels for the parallel interface pins are set in accordance with the specifications listed in Table ...
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SERIAL INTERFACE CONFIGURATION REGISTERS The serial interface configuration registers can be read and written using the I The least significant bits of the AD8197 I 3.3 V (Logic (Logic 0). As soon as the serial control ...
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AD8197 Table 9. Dual Mode, 2× [8:1], High Speed Switch Mapping HS_CH[3:0] O[3:2] O[1:0] Description X000 A1 A0 The A0 and A1 high speed channels switched to output X001 A3 A2 The A2 and A3 high speed channels switched to ...
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Table 14. Dual Mode, 2× [8:1], Auxiliary Switch Mapping AUX_CH[3:0] AUX_COM[3:2] AUX_COM[1:0] X000 AUX_C0 AUX_A0 X001 AUX_C1 AUX_A1 X010 AUX_C2 AUX_A2 X011 AUX_C3 AUX_A3 X100 AUX_D0 AUX_B0 X101 AUX_D1 AUX_B1 X110 AUX_D2 AUX_B2 X111 AUX_D3 AUX_B3 Table 15. Single Mode, ...
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AD8197 RECEIVER SETTINGS REGISTER RX_TO: High Speed (TMDS) Channels Input Termination On/Off Select Bit Table 16. RX_TO Description RX_TO Description 0 Input termination off 1 Input termination on (can be pulsed on and off according to settings in the input ...
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PARALLEL INTERFACE CONFIGURATION REGISTERS The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and PP_OCL pins. This interface is only accessible after the part is reset and before any registers are accessed using ...
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AD8197 RECEIVER SETTINGS REGISTER High speed (TMDS) channels input termination is fixed to on when using the parallel interface. INPUT TERMINATION PULSE REGISTER 1 AND REGISTER 2 High speed input (TMDS) channels pulse-on-source switching fixed to off when using the ...
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APPLICATION INFORMATION Figure 31. Layout of the TMDS Traces on the AD8197 Evaluation Board (Only Top Signal Routing Layer is Shown) The AD8197 is an HDMI/DVI switch, featuring equalized TMDS inputs and pre-emphasized TMDS outputs in- tended for ...
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AD8197 The length of cable that can be used in a typical HDMI/DVI application depends on a large number of factors, including: • Cable quality: the quality of the cable in terms of conductor wire gauge and shielding. Thicker conductors ...
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TMDS signals away from other signals and noise sources on the PCB. Both traces of a given differential pair must be equal in length to minimize intrapair skew. Maintaining the physical symmetry of a differential pair is ...
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AD8197 the AD8197 and do not need to be routed with the same strict considerations as the high speed TMDS signals. In general sufficient to route each auxiliary signal as a single-ended trace. These signals are not sensitive ...
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Power Supply Bypassing The AD8197 requires minimal supply bypassing. When powering the supplies individually, place a 0.01 μF capacitor between each 3.3 V supply pin (AVCC, DVCC, VTTI, and VTTO) and ground to filter out supply noise. Generally, bypass capacitors ...
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... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 AD8197ASTZ −40°C to +85°C 1 AD8197ASTZ-R7 −40°C to +85°C AD8197-EVAL Pb-free part. 16.20 16.00 SQ 1.60 MAX 15.80 0.75 100 1 0.60 0.45 PIN 1 TOP VIEW (PINS DOWN) 0 ...
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NOTES Rev Page AD8197 ...
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AD8197 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D60471-0-1/07(0) Rev Page ...