ADC1210S065HN/C1:5 NXP Semiconductors, ADC1210S065HN/C1:5 Datasheet - Page 15

• Manufacturer Part Number: ADC1210S065HN/C1:5
• Description: ADC1210S065HN/HVQFN40/REEL13DP
• Manufacturer: NXP Semiconductors

Specifications of ADC1210S065HN/C1:5

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935289036518; ADC1210S065HN,518; ADC1210S065HN,518

NXP Semiconductors
11. Application information
ADC1210S_SER
Product data sheet
11.1.1 SPI and Pin control modes
11.1.2 Operating mode selection
11.1.3
11.1 Device control
The ADC1210S can be controlled via SPI or directly via the I/O pins (Pin control mode).
The device enters Pin control mode at power-up, and remains in this mode as long as pin
CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device remains in this mode. The transition from Pin control mode to SPI
control mode is illustrated in
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO at the instant a transition is triggered by a falling
edge on pin CS.
The active ADC1210S operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see
described in
Table 10.
Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see
ODS is HIGH, otherwise CMOS is selected.
Pin PWD
LOW
LOW
HIGH
HIGH
Fig 15. Control mode selection
Table
Operating mode selection via pin PWD and OE
23) or by using pin ODS in Pin control mode. LVDS DDR is selected when
Table
SCLK/DFS
SDIO/ODS
All information provided in this document is subject to legal disclaimers.
10.
CS
Rev. 2 — 23 December 2010
Pin OE
LOW
HIGH
LOW
HIGH
two's complement
Table
Pin control mode
Data format
LVDS DDR
Figure
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
20) or by using pins PWD and OE in Pin control mode, as
15.
offset binary
Data format
Operating mode
Power-up
Power-up
Sleep
Power-down
CMOS
ADC1210S series
R/W
SPI control mode
W1
W0
005aaa039
Output high-Z
no
yes
yes
yes
A12
© NXP B.V. 2010. All rights reserved.
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