ADC1210S NXP Semiconductors, ADC1210S Datasheet
ADC1210S
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ADC1210S Summary of contents
Page 1
... Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1210S is ideal for use in communications, imaging and medical applications. 2. Features and benefits SNR, 70 dBFS ...
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... Block diagram INP INM Fig 1. Block diagram ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs Description no leads; 40 terminals; body 6 × 6 × 0. leads; 40 terminals; body 6 × 6 × 0. leads; 40 terminals; body 6 × 6 × 0. leads; 40 terminals; body 6 × 6 × 0.85 mm ...
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... Table 2. Symbol REFB REFT AGND VCM VDDA AGND INM INP AGND VDDA VDDA CLKP CLKM DEC OE PWD ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs terminal 1 index area REFB REFT 30 n.c. AGND 29 n.c. VCM 28 D0 VDDA 27 D1 AGND 26 D2 INM ...
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... D10_D11_P D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M D0_D1_P n.c. ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs Pin description (CMOS digital outputs) [1] Pin Type Description 17 O data output bit 11 (MSB data output bit data output bit 9 ...
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... Thermal characteristics Table 5. Symbol R th(j-a) R th(j-c) [1] Value for six layers board in still air with a minimum of 25 thermal vias. ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs Pin description (LVDS/DDR) digital outputs) [1] [2] Pin Type Description 30 - not connected 31 O data valid output clock, complement ...
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... HIGH-level input voltage IH I LOW-level input current IL I HIGH-level input current IH C input capacitance I ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs Conditions CMOS mode LVDS DDR mode f = 125 Msps; f =70 MHz clk i CMOS mode 125 Msps; clk f ...
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... Typical values measured DDA = −40 °C to +85 ° temperature range T amb CMOS and LVDS interface; unless otherwise specified. ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs …continued Conditions I = <tbd> <tbd> OH 3-state; output level = 0 V 3-state; output level = V high impedance ...
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... ADC1210S105 ADC1210S125 Unit Typ Max Min Typ Max dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... Max Min - °C and pF; minimum and maximum values are across the full temperature range T amb L ADC1210S105 ADC1210S125 Unit Typ Max Min Typ Max dBc dBc dBc dBc = −40 °C to +85 °C amb ...
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... pF; minimum and maximum values are across the full temperature range T amb L ADC1210S125 Unit Typ Max Min Typ Max - 105 100 - 125 MHz clock cycle 0 0 <tbd> ...
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... NXP Semiconductors CLKP CLKM DATA DAV Fig 4. CMOS mode timing Fig 5. LDVS DDR mode timing ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs d(s) t clk − 14) (N − 13 clk ...
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... SPI timing 11. Application information 11.1 Device control The ADC1210S can be controlled via SPI or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins ...
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... When the device enters SPI control mode, the output data standard and data format are determined by the level on pin SDIO at the instant a transition is triggered by a falling edge on CS. 11.1.2 Operating mode selection The active ADC1210S operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see described in Table 10. ...
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... Fig 9. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs Package ESD Parasitics 8 INP 7 INM ...
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... Fig 11. Dual transformer configuration suitable for high intermediate frequency application ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs RC coupling versus input frequency, typical values R 25 Ω 12 Ω 12 Ω ...
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... System reference and power management 11.3.1 Internal/external references The ADC1210S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable steps between 0 dB and −6 dB via control bits INTREF[2:0] when bit INTREF_EN = 1 ...
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... ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs to Figure 16 illustrate how to connect the SENSE and VREF pins to select the Fig 14. Internal reference (p-p) full-scale 005aaa119 Fig 16. Internal reference via SPI (p- (p-p) 22) ...
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... DDA 11.4 Clock input 11.4.1 Drive modes The ADC1210S can be driven differentially (SINE, LVPECL or LVDS) with little or no influence on the dynamic performances. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor). ...
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... Equivalent input circuit The equivalent circuit of the input clock buffer is shown in voltage of the differential input stage is set via internal 5 kΩ resistors. Fig 20. Equivalent input circuit ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs CLKP Sine clock input CLKM 005aaa173 ...
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... Clock input divider The ADC1210S contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed ...
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... Fig 23. LVDS DDR digital output buffer - internally terminated The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI[1:0] and DATAI[1:0]; see voltage levels. ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs 23). VCCO 3.5 mA typ − ...
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... However it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET[5:0]; see 11.5.6 Test patterns For test purposes, the ADC1210S can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see can be defined by the user (TESTPAT_USER; see when TESTPAT_SEL[2:0] = 101 ...
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... Serial peripheral interface 11.6.1 Register description The ADC1210S serial interface is a synchronous serial communications port that allows for easy interfacing with many commonly-used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin) Pin SCLK is the serial clock input and CS is the chip select pin ...
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... During circuit initialization, it does not matter which output data standard has been selected. At power-up, the device starts to Pin control mode. A falling edge on CS will trigger a transition to SPI control mode. When the ADC1210S enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by ...
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... NXP Semiconductors Fig 25. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR Fig 26. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs CS SDIO (CMOS LVDS DDR) CS ...
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Register allocation map Table 19. Register allocation map AddrHex Register name R/W Bit definition Bit 7 Bit 6 Bit 5 0005 Reset and R/W SW_RST operating mode 0006 Clock R/W - ...
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... Access SE_SEL R/W 3 DIF_SE R CLKDIV R/W 0 DCS_EN R/W ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs Value Description reset digital section 0 no reset 1 performs a reset of the digital section 000 reserved 00 not used operating mode 00 normal (power-up) 01 power-down 10 sleep ...
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... Output data standard control register (address 0011h) bit description Bit Symbol LVDS_CMOS 3 OUTBUF 2 OUTBUS_SWAP DATA_FORMAT[1:0] ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs Value Description 0000 not used programmable internal reference enable 0 disable 1 active programmable internal reference 000 −1 dB (FS = 1.78 V) 001 − ...
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... TESTPAT_SEL[2:0] Table 27. Test pattern register 2 (address 0015h) bit description Bit Symbol TESTPAT_USER[11:4] ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs Value Description 0000 not used output clock data valid (DAV) polarity 0 normal 1 inverted DAV phase select ...
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... CMOS output register (address 0020h) bit description Bit Symbol Access DAV_DRV[1:0] R DATA_DRV[1:0] R/W ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs Access Value Description R/W 0000 custom digital test pattern (bits 0000 not used Access Value Description 0000 not used ...
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... LVDS DDR output register 2 (address 0022h) bit description Bit Symbol BIT_BYTE_WISE LVDS_INTTER[2:0] ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs Value Description 00 not used double LVDS current for DAV LVDS buffer 0 disabled 1 enabled LVDS current for DAV LVDS buffer 00 3 ...
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... Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version IEC SOT618-6 Fig 27. Package outline SOT618-6 (HVQFN40) ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs 1 ...
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... Table 33. Revision history Document ID Release date ADC1210S_SER_1 20100409 ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs Data sheet status Change notice Preliminary data sheet - All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 April 2010 ADC1210S series www ...
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... ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs [3] Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. ...
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... For sales office addresses, please send an email to: ADC1210S_SER_1 Preliminary data sheet ADC1210S series; CMOS or LVDS DDR digital outputs NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... Out-of-Range (OTR 11.5.5 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.5.6 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.5.7 Output codes versus input voltage . . . . . . . . . 23 11.6 Serial peripheral interface 11.6.1 Register description . . . . . . . . . . . . . . . . . . . . 23 11.6.2 Default modes at start- ADC1210S series; CMOS or LVDS DDR digital outputs 11.6.3 Register allocation map . . . . . . . . . . . . . . . . . 26 12 Package outline Revision history . . . . . . . . . . . . . . . . . . . . . . . 33 14 Legal information . . . . . . . . . . . . . . . . . . . . . . 34 14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34 14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 14 ...