ADC1210S NXP Semiconductors, ADC1210S Datasheet - Page 21

• Manufacturer Part Number: ADC1210S
• Description: Single 12-bit ADC
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1210S_SER_1
Preliminary data sheet
11.5.2 Digital output buffers: LVDS DDR mode
The output resistance is 50 Ω and is the combination of the an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see
The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1
(see
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side
Table
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see
voltage levels.
Fig 22. LVDS DDR digital output buffer - externally terminated
Fig 23. LVDS DDR digital output buffer - internally terminated
(Figure
Table
32).
23).
22) or internally via SPI control bits LVDS_INT_TER[2:0] (see
All information provided in this document is subject to legal disclaimers.
−
+
−
+
Rev. 01 — 9 April 2010
3.5 mA
typ
3.5 mA
typ
ADC1210S series; CMOS or LVDS DDR digital outputs
100 Ω
+
+
−
−
VCCO
D
D
OGND
VCCO
D
D
OGND
n
n
x
x
P/D
M/D
P/D
M/D
Table
x + 1
n + 1
x + 1
n + 1
P
P
M
M
31) in order to adjust the output logic
ADC1210S series
100 Ω
RECEIVER
RECEIVER
005aaa058
005aaa059
© NXP B.V. 2010. All rights reserved.
Table
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Figure 23
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