ADC1210S NXP Semiconductors, ADC1210S Datasheet - Page 36

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ADC1210S

Manufacturer Part Number
ADC1210S
Description
Single 12-bit ADC
Manufacturer
NXP Semiconductors
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADC1210S080HN/C1:5
Manufacturer:
NXP
Quantity:
1 001
NXP Semiconductors
16. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
11
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.6
11.6.1
11.6.2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Application information. . . . . . . . . . . . . . . . . . 12
General description . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Clock and digital output timing . . . . . . . . . . . . 10
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Device control . . . . . . . . . . . . . . . . . . . . . . . . . 12
SPI and Pin control modes . . . . . . . . . . . . . . . 12
Operating mode selection. . . . . . . . . . . . . . . . 13
Selecting the output data standard . . . . . . . . . 13
Selecting the output data format. . . . . . . . . . . 13
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 14
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 15
System reference and power management . . 16
Internal/external references . . . . . . . . . . . . . . 16
Reference gain control . . . . . . . . . . . . . . . . . . 17
Common-mode output voltage (V
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 18
Equivalent input circuit . . . . . . . . . . . . . . . . . . 19
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 20
Clock input divider . . . . . . . . . . . . . . . . . . . . . 20
Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 20
Digital output buffers: CMOS mode . . . . . . . . 20
Digital output buffers: LVDS DDR mode . . . . . 21
Data valid (DAV) output clock . . . . . . . . . . . . . 22
Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 22
Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output codes versus input voltage . . . . . . . . . 23
Serial peripheral interface. . . . . . . . . . . . . . . . 23
Register description . . . . . . . . . . . . . . . . . . . . 23
Default modes at start-up . . . . . . . . . . . . . . . . 24
O(cm)
) . . . . . 18
ADC1210S series; CMOS or LVDS DDR digital outputs
11.6.3
12
13
14
14.1
14.2
14.3
14.4
15
16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 32
Revision history . . . . . . . . . . . . . . . . . . . . . . . 33
Legal information . . . . . . . . . . . . . . . . . . . . . . 34
Contact information . . . . . . . . . . . . . . . . . . . . 35
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Register allocation map . . . . . . . . . . . . . . . . . 26
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ADC1210S series
Document identifier: ADC1210S_SER_1
Date of release: 9 April 2010
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All rights reserved.

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