ADC1210S NXP Semiconductors, ADC1210S Datasheet - Page 20

• Manufacturer Part Number: ADC1210S
• Description: Single 12-bit ADC
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1210S_SER_1
Preliminary data sheet
11.4.3 Duty cycle stabilizer
11.4.4 Clock input divider
11.5.1 Digital output buffers: CMOS mode
11.5 Digital outputs
Single-ended or differential clock inputs can be selected via the SPI interface (see
Table
bit SE_SEL.
If single-ended is implemented without setting SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = 1; see
between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
The ADC1210S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = 1; see
clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0
(see
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in
supply, pins OGND and V
the ADC core. Each buffer can be loaded by a maximum of 10 pF.
Fig 21. CMOS digital output buffer
Table
21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control
23).
All information provided in this document is subject to legal disclaimers.
DRIVER
LOGIC
Rev. 01 — 9 April 2010
DDO
Table
, to ensure 1.8 V to 3.3 V compatibility and is isolated from
ADC1210S series; CMOS or LVDS DDR digital outputs
Figure
Table
21), the circuit can handle signals with duty cycles of
50 Ω
21). This feature allows the user to deliver a higher
21. The buffer is powered by a separate power
PARASITICS
ESD
ADC1210S series
PACKAGE
005aaa057
© NXP B.V. 2010. All rights reserved.
www.DataSheet4U.com
VDDO
Dx
OGND
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