ADC1210S065HN/C1:5 NXP Semiconductors, ADC1210S065HN/C1:5 Datasheet - Page 39

• Manufacturer Part Number: ADC1210S065HN/C1:5
• Description: ADC1210S065HN/HVQFN40/REEL13DP
• Manufacturer: NXP Semiconductors

Specifications of ADC1210S065HN/C1:5

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935289036518; ADC1210S065HN,518; ADC1210S065HN,518

NXP Semiconductors
16. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
10.4
11
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.2
11.2.1
11.2.2
11.2.3
11.3
11.3.1
11.3.2
11.3.3
11.3.4
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.5.7
11.6
11.6.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal characteristics . . . . . . . . . . . . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Application information. . . . . . . . . . . . . . . . . . 15
Clock and digital output timing . . . . . . . . . . . . . 9
Device control . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating mode selection. . . . . . . . . . . . . . . . 15
Selecting the output data format. . . . . . . . . . . 16
Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 16
Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Programmable full-scale . . . . . . . . . . . . . . . . . 20
Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 21
Equivalent input circuit . . . . . . . . . . . . . . . . . . 22
Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 23
Digital output buffers: CMOS mode . . . . . . . . 23
Digital output buffers: LVDS DDR mode . . . . . 24
DAta Valid (DAV) output clock . . . . . . . . . . . . 25
Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 25
Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output codes versus input voltage . . . . . . . . . 26
Serial peripheral interface. . . . . . . . . . . . . . . . 26
Register description . . . . . . . . . . . . . . . . . . . . 26
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical characteristics . . . . . . . . . . . . . . . . . . 13
SPI and Pin control modes . . . . . . . . . . . . . . . 15
Selecting the output data standard . . . . . . . . . 15
Anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 16
System reference and power management . . 18
Internal/external references . . . . . . . . . . . . . . 18
Common-mode output voltage (V
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 23
Clock input divider . . . . . . . . . . . . . . . . . . . . . 23
O(cm)
) . . . . . 21
Single 12-bit ADC; CMOS or LVDS DDR digital outputs
11.6.2
11.6.3
12
13
14
14.1
14.2
14.3
14.4
15
16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 35
Revision history . . . . . . . . . . . . . . . . . . . . . . . 36
Legal information . . . . . . . . . . . . . . . . . . . . . . 37
Contact information . . . . . . . . . . . . . . . . . . . . 38
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Default modes at start-up. . . . . . . . . . . . . . . . 27
Register allocation map . . . . . . . . . . . . . . . . . 29
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ADC1210S series
Document identifier: ADC1210S_SER
Date of release: 23 December 2010
All rights reserved.