ADF7021-VBCPZ-RL Analog Devices Inc, ADF7021-VBCPZ-RL Datasheet - Page 15

• Manufacturer Part Number: ADF7021-VBCPZ-RL
• Description: Narrow Band Transceiver 433/868/900 MHz
• Manufacturer: Analog Devices Inc

Specifications of ADF7021-VBCPZ-RL

• Frequency: 80MHz ~ 960MHz
• Data Rate - Maximum: 24 kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 13dBm
• Sensitivity: -125dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 21.7mA
• Current - Transmitting: 27.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12, 19, 22
13 to 16
17, 18, 20,
21
23
24
25
26
Mnemonic
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RFIN
R
VDD4
RSET
CREG4
GND4
MIX_I, MIX_I,
MIX_Q, MIX_Q
FILT_I, FILT_I,
FILT_Q, FILT_Q,
TEST_A
CE
SLE
SDATA
LNA
Do not connect.
Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and
ground for regulator stability and noise rejection.
Voltage Supply for PA Block. Place decoupling capacitors of 0.1 μF and 100 pF as close as possible to this
pin. Tie all VDDx pins together.
The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The
output should be impedance matched to the desired load using suitable components.
Ground for Output Stage of Transmitter. Tie all GND pins together.
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer.
Complementary LNA Input.
External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
Voltage Supply for LNA/Mixer Block. Decouple this pin to ground with a 10 nF capacitor. Tie all VDDx pins
together.
External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with
5% tolerance.
Regulator Voltage for LNA/Mixer Block. Place a 100 nF capacitor between this pin and ground for
regulator stability and noise rejection.
Ground for LNA/Mixer Block. Tie all GND pins together.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Signal Chain Test Pin. This pin is high impedance under normal conditions and should be left unconnected.
Chip Enable. Bringing CE low puts the ADF7021-V into complete power-down. Register values are lost
when CE is low, and the part must be reprogrammed after CE is brought high.
Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of
the 16 latches. A latch is selected using the control bits.
Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This pin is a
high impedance CMOS input.
Description
RFGND
NOTES
1. THE EXPOSED PADDLE MUST BE CONNECTED
CREG1
RFOUT
CREG4
VCOIN
GND4
VDD1
VDD4
RSET
R
TO THE GROUND PLANE.
RFIN
RFIN
LNA
10
11
12
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Figure 10. Pin Configuration
Rev. 0 | Page 15 of 60
ADF7021-V
(Not to Scale)
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
CLKOUT
SWD
VDD2
CREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE
TxRxCLK
TxRxDATA
ADF7021-V