ADF7021-VBCPZ-RL Analog Devices Inc, ADF7021-VBCPZ-RL Datasheet - Page 59

• Manufacturer Part Number: ADF7021-VBCPZ-RL
• Description: Narrow Band Transceiver 433/868/900 MHz
• Manufacturer: Analog Devices Inc

Specifications of ADF7021-VBCPZ-RL

• Frequency: 80MHz ~ 960MHz
• Data Rate - Maximum: 24 kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 13dBm
• Sensitivity: -125dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 21.7mA
• Current - Transmitting: 27.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 15—TEST MODE REGISTER
•
•
Analog RSSI can be viewed on the TEST_A pin by setting
ANALOG_TEST_MODES (Bits[DB27:DB24]) to 11.
Tx_TEST_MODES can be used to enable modulation test.
COx
0
1
2
3
AMx
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CAL_OVERRIDE
AUTO CAL
OVERRIDE GAIN
OVERRIDE BW
OVERRIDE BW AND GAIN
OFFSET LOOP +VE FBACK V (I CH)
SUMMED OUTPUT OF RSSI RECTIFIER+
SUMMED OUTPUT OF RSSI RECTIFIER–
BIAS CURRENT FROM BB FILTER
ANALOG_TEST_MODES
BAND GAP VOLTAGE
40µA CURRENT FROM REG4
FILTER I CHANNEL: STAGE 1
FILTER I CHANNEL: STAGE 2
FILTER I CHANNEL: STAGE 1
FILTER Q CHANNEL: STAGE 1
FILTER Q CHANNEL: STAGE 2
FILTER Q CHANNEL: STAGE 1
ADC REFERENCE VOLTAGE
BIAS CURRENT FROM RSSI 5µA
FILTER COARSE CAL OSCILLATOR OUTPUT
ANALOG RSSI I CHANNE
RD1
0
1
PMx
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
REG1_PD
NORMAL
POWER-DOWN
ANALOG_TEST_
PLL_TEST_MODES
NORMAL OPERATION
R DIV
N DIV
RCNTR/2 ON MUXOUT
NCNTR/2 ON MUXOUT
ACNTR TO MUXOUT
PFD PUMP UP TO MUXOUT
PFD PUMP DNTO MUXOUT
S DATA TO MUXOUT (OR SREAD)
ANALOG LOCK DETECT ON MUXOUT
END OF COARSE CAL ON MUXOUT
END OF FINE CAL ON MUXOUT
FORCE NEW PRESCALER CONFIG
FOR ALL N
TEST MUX SELECTS DATA
LOCK DETECT PRECISION
RESERVED
FH1
0
1
L
MODES
FORCE_LD_HIGH
NORMAL
FORCE
PLL_TEST_
MODES
Figure 77. Register 15—Test Mode Register Map
CMx
0
1
2
3
4
5
6
7
NORMAL, NO OUTPUT
DEMOD CLK
CDR CLK
SEQ CLK
BB OFFSET CLK
Σ-Δ CLK
ADC CLK
TxRxCLK
CLK_MUX ON CLKOUT PIN
CLK_MUX
PCx
0
1
2
3
4
5
6
7
Rev. 0 | Page 59 of 60
SDx
0
1
2
3
4
5
6
7
PFD/CP_TEST_MODES
DEFAULT, NO BLEED
(+VE) CONSTANT BLEED
(–VE) CONSTANT BLEED
(–VE) PULSED BLEED
(–VE) PULSE BLD, DELAY UP
CP PUMP UP
CP TRISTATE
CP PUMP DN
Σ-Δ_TEST_MODES
DEFAULT, 3RD-ORDER Σ-Δ, NO DITHER
1ST-ORDER Σ-Δ
2ND-ORDER Σ-Δ
DITHER TO FIRST STAGE
DITHER TO SECOND STAGE
DITHERTO THIRD STAGE
DITHER × 8
DITHER × 32
TEST_MODES
PFD/CP_
•
TMx
0
1
2
3
4
5
6
The CDR block can be bypassed by setting Rx_TEST_
MODES to 4, 5, or 6, depending on the demodulator used.
Σ-Δ_TEST_
MODES
Tx_TEST_MODES
NORMAL OPERATION
Tx CARRIER ONLY
Tx +
Tx –
Tx "1010" PATTERN
Tx PN9 DATA SEQUENCE
Tx SWD PATTERN REPEATEDLY
f
f
DEV
DEV
TONE ONLY
TONE ONLY
RTx
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Tx_TEST_
MODES
Rx_TEST_MODES
NORMAL
SCLK, SDATA
REVERSE I,Q
CORRELATOR SLICER ON TxRxDATA
LINEAR SLICER ON TxRxDATA
SDATA TO CDR
ADDITIONAL FILTERING ON I,Q
ENABLE REG 14 DEMOD PARAMETERS
POWER DOWN DDT AND ED IN T/4 MODE
ENVELOPE DETECTOR WATCHDOG DISABLED
RESERVED
PROHIBIT CAL ACTIVE
FORCE CAL ACTIVE
ENABLE DEMOD DURING CAL
I,Q TO TxRxCLK, TxRxDATA
3FSK SLICER ON TxRxDATA
Rx_TEST_
MODES
I,Q
ADF7021-V
ADDRESS
BITS