ADF7021-VBCPZ-RL Analog Devices Inc, ADF7021-VBCPZ-RL Datasheet - Page 4

• Manufacturer Part Number: ADF7021-VBCPZ-RL
• Description: Narrow Band Transceiver 433/868/900 MHz
• Manufacturer: Analog Devices Inc

Specifications of ADF7021-VBCPZ-RL

• Frequency: 80MHz ~ 960MHz
• Data Rate - Maximum: 24 kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 13dBm
• Sensitivity: -125dBm
• Voltage - Supply: 2.3 V ~ 3.6 V
• Current - Receiving: 21.7mA
• Current - Transmitting: 27.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF7021-V
SPECIFICATIONS
V
measurements are performed with the EVAL-ADF7021-VDBxZ using the PN9 data sequence, unless otherwise noted. The version
number of ETSI EN 300 200-1 is V2.3.1. LBW = loop bandwidth and IFBW = IF filter bandwidth.
RF AND PLL SPECIFICATIONS
Table 1.
Parameter
RF CHARACTERISTICS
PHASE-LOCKED LOOP (PLL)
EXTERNAL VCO
REFERENCE INPUT
ADC PARAMETERS
1
2
3
4
This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance
as seen at the power amplifier (PA) output: −203 + 10 log(f
Guaranteed by design. Sample tested to ensure compliance.
A TCXO, VCXO, or OCXO can be used as an external oscillator.
Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin.
DD
Phase Frequency Detector (PFD)
Normalized In-Band Phase Noise
PLL Settling
Tuning Range
Pin L2 Input Sensitivity
Crystal Reference
External Oscillator
Crystal Start-Up Time
Input Level for External Oscillator
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
= 2.3 V to 3.6 V, GND = 0 V, T
Frequency
Floor
XTAL Bias = 20 μA
XTAL Bias = 35 μA
OSC1 Pin
OSC2 Pin
1
2
2, 3
4
A
= T
MIN
Min
RF/256
0.2
0
3.625
3.625
to T
MAX
PFD
, unless otherwise noted. Typical specifications are at V
) + 20 logN.
CMOS levels
Typ
−203
155
0.930
0.438
0.8
±0.4
±0.4
Rev. 0 | Page 4 of 60
Max
24
2
24
24
Unit
MHz
dBc/Hz
μs
V
dBm
MHz
MHz
ms
ms
V p-p
V
LSB
LSB
Test Conditions/Comments
Maximum usable PFD at a particular RF frequency
is limited by the minimum N divider value
Measured for a 100 kHz frequency step to within
5 ppm accuracy, PFD = 19.68 MHz, LBW = 8 kHz
VCO frequency < 1920 MHz
10 MHz XTAL, 33 pF load capacitors, V
Clipped sine wave
V
DD
= 2.3 V to 3.6 V, T
DD
= 3 V, T
A
= 25°C
A
= 25°C. All
DD
= 3.0 V