ADUC7036DCPZ-RL Analog Devices Inc, ADUC7036DCPZ-RL Datasheet - Page 120

• Manufacturer Part Number: ADUC7036DCPZ-RL
• Description: SFlash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036DCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-VFQFN Exposed Pad, CSP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADuC7036
LIN Hardware Synchronization Timer0 Register
Name: LHSVAL0
Address: 0xFFFF0788
Default Value: 0x0000
Access: Read only
Function: This 16-bit, read only register holds the value of the
internal LIN synchronization timer. The LIN synchronization
timer is clocked from an internal 5 MHz clock and is indepen-
dent of core clock and baud rate frequency. In LIN mode, the value
read by user code from the LHSVAL0 register can be used to
calculate the master LIN baud rate. This calculation is then used
to configure the internal UART baud rate to ensure correct LIN
communication via the UART from the ADuC7036 slave to the
LIN master node.
LIN Hardware Synchronization Break Timer1 Register
Name: LHSVAL1
Address: 0xFFFF0790
Default Value: 0x0000
Access: Read/write
Function: When user code reads this location, the 12-bit value
returned is the value of the internal LIN break timer, which is
clocked directly from the on-chip low power 131 kHz oscillator
and times the LIN break pulse. A negative edge on the LIN bus
or user code reading the LHSVAL1 results in the timer and the
register contents being reset to 0.
When user code writes to this location, the 12-bit value is written
not to the LIN break timer but to a LIN break compare register.
In LIN mode of operation, the value in the compare register is
continuously compared to the break timer value. A LIN break
interrupt (IRQEN[7] and LHSSTA[0]) is generated when the
timer value reaches the compare value. After the break condition
interrupt, the LIN break timer continues to count until the
rising edge of the break signal. If a rising edge is not detected
and the 12-bit timer overflows (4096 × 1/131 kHz = 31 ms),
a break field error interrupt (IRQEN[7] and LHSSTA[4]) is
generated. By default, the value in the compare register is 0x0047,
corresponding to 11 bit periods (that is, the minimum pulse
width for a LIN break pulse at 20 kbps). For different baud rates,
this value can be changed by writing to LHSVAL1. Note that if
a valid break interrupt is not received, subsequent sync pulse
timing through the LHSVAL0 register does not occur.
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LIN HARDWARE INTERFACE
LIN Frame Protocol
The LIN frame protocol is broken into four main categories:
break symbol, sync byte, protected identifier, and data bytes.
The format of the frame header, break symbol, synchronization
byte, and protected identifier is shown in Figure 47. Essentially,
the embedded UART, the LIN hardware synchronization logic,
and the high voltage transceiver interface all combine on chip to
support and manage LIN-based transmissions and receptions.
LIN Frame Break Symbol
As shown in Figure 48, the LIN break symbol, which lasts at
least 13 bit periods, is used to signal the start of a new frame. The
slave must be able to detect a break symbol even while expecting or
receiving data. The ADuC7036 accomplishes this by using the
LHSVAL1 break condition and break error detect functionality
as described in the LIN Hardware Synchronization Break
Timer1 Register section. The break period does not have to be
accurately measured, but if a bus fault condition (bus held low)
occurs, it must be flagged.
LIN Frame Synchronization Byte
The baud rate of the communication using LIN is calculated
from the sync byte, as shown in Figure 49. The time between
the first falling edge of the sync field and the fifth falling edge
of the sync field is measured and then divided by 8 to determine
the baud rate of the data that is to be transmitted. The ADuC7036
implements the timing of this sync byte in hardware. For more
information about this feature, see the LIN Hardware
Synchronization Status Register section.
LIN Frame Protected Identifier
After receiving the LIN sync field, the required baud rate for the
UART is calculated. The UART is then configured, allowing the
ADuC7036 to receive the protected identifier, as shown in
Figure 50. The protected identifier consists of two subfields: the
identifier and the identifier parity. The 6-bit identifier contains
the identifier of the target for the frame. The identifier signifies
the number of data bytes to be either received or transmitted. The
number of bytes is user configurable at the system-level design.
The parity is calculated on the identifier and is dependent on
the revision of LIN for which the system is designed.
LIN Frame Data Byte
The data byte frame carries between one and eight bytes of data.
The number of bytes contained in the frame is dependent on
the LIN master. The data byte frame is split into data bytes, as
shown in Figure 51.