ADUC7036DCPZ-RL Analog Devices Inc, ADUC7036DCPZ-RL Datasheet - Page 21

• Manufacturer Part Number: ADUC7036DCPZ-RL
• Description: SFlash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036DCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-VFQFN Exposed Pad, CSP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ARM7 Exceptions
The ARM7 supports five types of exceptions with a privileged
processing mode associated with each type. The five types of
exceptions are as follows:
•
•
•
•
•
Typically, the programmer defines interrupts as IRQ, but for
higher priority interrupts, the programmer can define interrupts
as the FIQ type.
The priority of these exceptions and vector address are listed in
Table 9.
Table 9. Exception Priorities and Vector Addresses
Priority
1
2
3
4
5
6
6
1
The list of exceptions in Table 9 are located from 0x00 to 0x1C,
with a reserved location at 0x14. This location is required to be
written with either 0x27011970 or the checksum of Page 0,
excluding Location 0x14. If this is not done, user code does not
execute and LIN download mode is entered.
ARM Registers
The ARM7TDMI has 16 standard registers. R0 to R12 are used
for data manipulation, R13 is the stack pointer, R14 is the link
register, and R15 is the program counter that indicates the
instruction currently being executed. The link register contains
the address from which the user has branched (if the branch
and link command was used) or the command during which an
exception occurred.
The stack pointer contains the current location of the stack. As
a general rule, on an ARM7TDMI, the stack starts at the top of
the available RAM area and descends using the area as required.
A separate stack is defined for each of the exceptions. The size of
each stack is user configurable and is dependent on the target
application. On the ADuC7036, the stack begins at 0x00040FFC
A software interrupt and an undefined instruction exception have the same
priority and are mutually exclusive.
Normal interrupt or IRQ. This is provided to service
general-purpose interrupt handling of internal and
external events.
Fast interrupt or FIQ. This is provided to service data
transfer or a communication channel with low latency.
FIQ has priority over IRQ.
Memory abort (prefetch and data).
Attempted execution of an undefined instruction.
Software interrupt (SWI) instruction that can be used to
make a call to an operating system.
Exception
Hardware reset
Memory abort (data)
FIQ
IRQ
Memory abort (prefetch)
Software interrupt
Undefined instruction
1
1
Address
0x00
0x10
0x1C
0x18
0x0C
0x08
0x04
Rev. C | Page 21 of 132
and descends. When programming using high level languages,
such as C, it is necessary to ensure that the stack does not overflow.
This is dependent on the performance of the compiler that is used.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented
in Figure 11. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, thereby
reducing the response time of the interrupt handling process.
More information relative to the model of the programmer and
the ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.
Interrupt Latency
The worst-case latency for an FIQ consists of the longest possible
time for the request to pass through the synchronizer, for the
longest instruction to complete (the longest instruction is an LDM)
and load all the registers including the PC, and for the data abort
entry and the FIQ entry to complete. At the end of this time, the
ARM7TDMI executes the instruction at Address 0x1C (the FIQ
interrupt vector address). The maximum FIQ latency is 50 pro-
cessor cycles or just over 2.44 μs in a system using a continuous
20.48 MHz processor clock.
The maximum IRQ latency calculation is similar but must allow
for the fact that FIQ has higher priority and may delay entry into
the IRQ handling routine for an arbitrary length of time. This
time can be reduced to 42 cycles if the LDM command is not
used; some compilers have an option to compile without using
this command. Another option is to run the part in Thumb
mode, which reduces the time to 22 cycles.
USER MODE
R15 (PC)
CPSR
R10
R11
R12
R13
R14
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
SPSR_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
Figure 11. Register Organization
R8_FIQ
R9_FIQ
MODE
FIQ
SPSR_SVC
R13_SVC
R14_SVC
MODE
SVC
SPSR_ABT
R13_ABT
R14_ABT
ABORT
MODE
USABLE IN USER MODE
SYSTEM MODES ONLY
SPSR_IRQ
R13_IRQ
R14_IRQ
MODE
IRQ
ADuC7036
UNDEFINED
SPSR_UND
R13_UND
R14_UND
MODE