ADUC7036DCPZ-RL Analog Devices Inc, ADUC7036DCPZ-RL Datasheet - Page 127

• Manufacturer Part Number: ADUC7036DCPZ-RL
• Description: SFlash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036DCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-VFQFN Exposed Pad, CSP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

BSD DATA RECEPTION
To receive data, the LIN/BSD peripheral must first be con-
figured in BSD mode where LHSCON0[6] = 1. In this mode,
LHSCON0[8] should be set to ensure that the LHS break timer
(see the LIN Hardware Synchronization Break Timer1 Register
section) generates an interrupt on the rising edge of the BSD bus.
The LHS break timer is cleared and starts counting on the falling
edge of the BSD bus; the timer is subsequently stopped and
generates an interrupt on the rising edge of the BSD bus. Given
that the LHS break timer is clocked by the low power 131 kHz
oscillator, the value in LHSVAL1 can be interpreted by user code
to determine if the received data bit is a BSD sync pulse, 0, or 1.
1
LHSVAL1 CLEARED
AND STARTS COUNTING
ON THIS EDGE
BSD PERIOD
IN 0 STATE
RECEIVE SECOND
RECEIVE DATA
FROM MASTER
Figure 57. BSD Slave Node State Machine
PARITY BIT
Figure 58. Master Transmit, Slave Read
SYNCHRONIZATION
2
RECEIVE FIRST
INITIALIZE BSD
HARDWARE/
LHSVAL1 STOPPED
AND GENERATES
INTERRUPT ON THIS EDGE
SOFTWARE
DIRECTION
PARITY BIT
ACK/NACK
REGISTER
TRANSMIT
ADDRESS
ADDRESS
RECEIVE
RECEIVE
RECEIVE
RECEIVE
PULSES
SLAVE
BIT
BSD PERIOD
IN 1 STATE
TRANSMIT SECOND
TRANSMIT DATA
TO MASTER
PARITY BIT
Rev. C | Page 127 of 132
BSD DATA TRANSMISSION
User code forces the GPIO_12 signal low for a specified time to
transmit data in BSD mode. In addition, user code uses the sync
timer (LHSVAL0), the LHS sync capture register (LHSCAP), and
the LHS sync compare register (LHSCMP) to determine the
length of time that the BSD bus should be held low for bit
transmissions in the 0 or 1 state.
As described in the BSD Example Pulse Widths section, even
when the slave is transmitting, the master always starts the bit
transmission period by pulling the BSD bus low. If BSD mode
is selected (LHSCON0[6] = 1), the LIN sync timer value is
captured in LHSCAP on every falling edge of the BSD bus.
The LIN sync timer runs continuously in BSD mode.
Then, user code can immediately force GPIO_12 low and read
the captured timer value from LHSCAP. Next, the user can calcu-
late how many clock periods (with a 5 MHz clock) should elapse
before the GPIO_12 is driven high for a pulse width in the 0 or
1 state. The calcaulated number can be added to the LHSCAP
value and written into the LHSCMP register. If LHSCON0[5] is
set, the sync timer, which continues to count (being clocked by
a 5 MHz clock), eventually equals the LHSCMP value and
generates an LHS compare interrupt (LHSSTA[3]).
The response to this interrupt should be to force the GPIO_12
signal (and, therefore, the BSD bus) high. The software control
of the GPIO_12 signal, along with the correct use of the LIN
synchronization timers, ensures that valid pulse widths in the
0 and 1 states can be transmitted from the ADuC7036, as shown
in Figure 59. Again, care must be taken if switching from BSD
write mode to BSD read mode, as described in Table 93 (see the
LHSCON0[8] bit.)
WAKE-UP FROM BSD INTERFACE
The MCU core can be awakened from power-down via the BSD
physical interface. Before entering power-down mode, user code
should enable the start condition interrupt (LHSCON0[3]). When
this interrupt is enabled, a high-to-low transition on the LIN/BSD
pin generates an interrupt event and wakes up the MCU core.
2
1
LHSVAL0 LOADED
INTO LHSCAP HERE
MASTER DRIVES
BSD BUS LOW
BSD PERIOD
IN 0 STATE
Figure 59. Master Read, Slave Transmit
3
4
SOFTWARE ASSERTS
BSD LOW HERE
LHSCMP = LHSVAL0
INTERRUPT GENERATED
HERE
5
SOFTWARE DEASSERTS
BSD HIGH HERE
BSD PERIOD
IN 1 STATE
ADuC7036