ADUC7036DCPZ-RL Analog Devices Inc, ADUC7036DCPZ-RL Datasheet - Page 35

• Manufacturer Part Number: ADUC7036DCPZ-RL
• Description: SFlash 96k ARM7 Dual 16-Bit ADC LIN I.C.
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7036DCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-VFQFN Exposed Pad, CSP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
top 4 kB of the MCU memory space and accessed by indirect
addressing, loading, and storage commands through the ARM7
banked registers. An outline of the memory mapped register
bank for the ADuC7036 is shown in Figure 17.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the ARM7 core registers
(described in the ARM Registers section) reside in the MMR area.
As shown in Table 19 to Table 30 in the Complete MMR Listing
section, the MMR data widths vary from one byte (eight bits) to
four bytes (32 bits). The ARM7 core can access any of the MMRs
(single byte or multiple byte width registers) with a 32-bit read
or write access.
The resultant read, for example, is aligned per little endian format,
as described in the ARM Registers section. However, errors result
if the ARM7 core tries to access 4-byte (32-bit) MMRs with
a 16-bit access. In the case of a 16-bit write access to a 32-bit
MMR, the 16 most significant bits (the upper 16 bits) are
written as 0s. The case of a 16-bit read access to a 32-bit MMR,
only 16 of the MMR bits can be read.
Rev. C | Page 35 of 132
0xFFFFFFFF
0xFFFF0D50
0xFFFF0D00
0xFFFF0A14
0xFFFF0A00
0xFFFF079C
0xFFFF044C
0xFFFF0E00
0xFFFF1000
0xFFFF0894
0xFFFF0880
0xFFFF0810
0xFFFF0800
0xFFFF0780
0xFFFF0730
0xFFFF0700
0xFFFF0580
0xFFFF0500
0xFFFF0400
0xFFFF0394
0xFFFF0380
0xFFFF0370
0xFFFF0360
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
0xFFFF0318
0xFFFF0300
0xFFFF0244
0xFFFF0220
0xFFFF0110
0xFFFF0000
Figure 17. Top-Level MMR Map
OSCILLATOR CONTROL
GENERAL-PURPOSE
GENERAL-PURPOSE
SYSTEM CONTROL
FLASH CONTROL
HV INTERFACE
CONTROLLER
SERIAL TEST
WATCHDOG
REMAP AND
HARDWARE
INTERFACE
INTERFACE
INTERRUPT
WAKE-UP
PLL AND
LIN/BSD
TIMER4
TIMER3
TIMER2
TIMER1
TIMER0
UART
GPIO
ADC
SPI
ADuC7036