CS8416-DZZR Cirrus Logic Inc, CS8416-DZZR Datasheet - Page 10

• Manufacturer Part Number: CS8416-DZZR
• Description: IC,Digital Audio Receiver,CMOS,TSSOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

10
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
Notes:
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dic-
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For f
tated by the timing requirements necessary to access the Channel Status memory. Access to the con-
trol register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is
32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible conditions.
sck
<1 MHz.
Parameter
CDOUT
CDIN
CCLK
CS
t css
L
t r2
= 20 pF)
Figure 3. SPI Mode Timing
t dsu
t scl
(Note 12)
(Note 13)
(Note 14)
(Note 14)
t f2
t sch
t dh
Symbol
t pd
t
t
f
t
t
t
t
t
csh
sch
dsu
t
t
t
t
sck
css
scl
dh
pd
r1
r2
r2
f1
Min
1.0
20
66
66
40
15
0
-
-
-
-
-
t csh
Max
100
100
6.0
50
25
25
-
-
-
-
-
-
CS8416
DS578F3
MHz
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns