CS8416-DZZR Cirrus Logic Inc, CS8416-DZZR Datasheet - Page 36

• Manufacturer Part Number: CS8416-DZZR
• Description: IC,Digital Audio Receiver,CMOS,TSSOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

36
14. CONTROL PORT REGISTER DESCRIPTIONS
14.1
14.2
(HEX)
Addr
1E
1F
20
21
22
23
24
25
26
7F
7
0
7
0
R/W
Memory Address Pointer (MAP)
Not a register
MAP[6:0] - Memory Address Pointer. Will automatically increment after each read or write.
Control0 (00h)
FSWCLK – Forces the clock signal on OMCK to be output on RMCK regardless of the SWCLK (Control1
register bit 6) bit functionality or PLL lock.
Default = ‘0’
0 – Clock signal on OMCK is output on RMCK according to the SWCLK bit functionality.
1 – Forces the clock signal on OMCK to be output on RMCK regardless of the SWCLK bit functionality.
PDUR – Changes the type of phase detector used to lock to the active RXP[7:0] input. This bit should only
be set if the sample rate range is between 32 kHz and 108 kHz. If the sample rate is outside of this range
and the PDUR bit is set, loss of lock may occur.
Default = ‘0’
0 – Normal Update Rate Phase Detector - Recovered master clock (RMCK) will have low wide-band jitter,
but increased in-band jitter.
R
R
R
R
R
R
R
R
R
R
Default = ‘0000000’
Burst Preamble PC
Burst Preamble PC
Burst Preamble PD
Burst Preamble PD
Channel B Status
Channel B Status
Channel B Status
Channel B Status
Channel B Status
ID & Version
Function
FSWCLK
MAP6
Byte 0
Byte 1
Byte 0
Byte 1
6
6
BC0[7]
BC1[7]
BC2[7]
BC3[7]
BC4[7]
PC0[7]
PC1[7]
PD0[7]
PD1[7]
MAP5
ID3
7
5
5
0
BC0[6]
BC1[6]
BC2[6]
BC3[6]
BC4[6]
PC0[6]
PC1[6]
PD0[6]
PD1[6]
ID2
6
MAP4
4
0
4
BC0[5]
BC1[5]
BC2[5]
BC3[5]
BC4[5]
PC0[5]
PC1[5]
PD0[5]
PD1[5]
ID1
5
PDUR
MAP3
3
BC0[4]
BC1[4]
BC2[4]
BC3[4]
BC4[4]
PC0[4]
PC1[4]
PD0[4]
PD1[4]
3
ID0
4
BC0[3]
BC1[3]
BC2[3]
BC3[3]
BC4[3]
PC0[3]
PC1[3]
PD0[3]
PD1[3]
VER3
TRUNC
MAP2
3
2
2
BC0[2]
BC1[2]
BC2[2]
BC3[2]
BC4[2]
PC0[2]
PC1[2]
PD0[2]
PD1[2]
VER2
2
Reserved
MAP1
1
1
BC0[1]
BC1[1]
BC2[1]
BC3[1]
BC4[1]
PC0[1]
PC1[1]
PD0[1]
PD1[1]
VER1
1
Reserved
CS8416
MAP0
DS578F3
BC0[0]
BC1[0]
BC2[0]
BC3[0]
BC4[0]
PC0[0]
PC1[0]
PD0[0]
PD1[0]
VER0
0
0
0