CS8416-DZZR Cirrus Logic Inc, CS8416-DZZR Datasheet - Page 30

• Manufacturer Part Number: CS8416-DZZR
• Description: IC,Digital Audio Receiver,CMOS,TSSOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

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10.ERROR AND STATUS REPORTING
10.1
10.1.1 Software Mode
10.1.2 Hardware Mode
General
While decoding the incoming bi-phase encoded data stream, the CS8416 has the ability to identify various
error conditions.
Software Mode allows the most flexibility in reading errors. When unmasked, bits in the Receiver Error
register (0Ch) indicate the following errors:
1. QCRC – CRC error in Q subcode data.
2. CCRC – CRC error in channel status data.
3. UNLOCK – PLL is not locked to incoming data stream.
4. V – Data Validity bit is set.
5. CONF – The logical OR of UNLOCK and BIP. The input data stream may be near error condition due
6. BIP – Biphase encoding error.
7. PAR – Parity error in incoming data.
The error bits are “sticky,” meaning that they are set on the first occurrence of the associated error and
will remain set until the user reads the register through the control port. This enables the register to log all
unmasked errors that occurred since the last time the register was read.
As a result of the bits “stickiness,” it is necessary to perform two reads on these registers to see if the error
condition still exists.
The Receiver Error Mask register (06h) allows masking of individual errors. The bits in this register default
to 00h and serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set to
1, the error is unmasked, which implies the following: its occurrence will be reported in the receiver error
register, induce a pulse on RERR, invoke the occurrence of a RERR interrupt, and affect the current audio
sample according to the status of the HOLD bits. The exceptions are the QCRC and CCRC errors, which
do not affect the current audio sample, even if unmasked.
The HOLD bits allow a choice of:
•
•
OR
•
In Hardware Mode, the user may only choose between Non-Validity Receiver Error (NVERR) or Receiver
Error (RERR) by pulling the NV/RERR pin low or high, respectively. The pull-up/pull-down condition will
be sensed on start-up, and the appropriate error reporting will be set.
RERR – The previous audio sample is held and passed to the serial audio output port if the validity bit is
high, or a parity, bi-phase, confidence or PLL lock error occurs during the current sample.
NVERR – The previous audio sample is held and passed to the serial audio output port if a parity, bi-
phase, confidence or PLL lock error occurs during the current sample.
Holding the previous sample
Replacing the current sample with zero (mute)
Not changing the current audio sample
to jitter degradation.
CS8416
DS578F3