CS8416-DZZR Cirrus Logic Inc, CS8416-DZZR Datasheet - Page 27

• Manufacturer Part Number: CS8416-DZZR
• Description: IC,Digital Audio Receiver,CMOS,TSSOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

DS578F3
8. S/PDIF RECEIVER
The CS8416 includes an AES3/SPDIF digital audio receiver. The receiver accepts and decodes bi-phase encoded
audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The re-
ceiver consists of an analog differential input stage, driven through analog input pins RXP0 to RXP7 and a common
RXN, a PLL based clock recovery circuit, and a decoder which separates the audio data from the channel status
and user data. External components are used to terminate the incoming data cables and isolate the CS8416. These
components are detailed in
the input structure of the receiver.
8.1
8.1.1
8.1.2
R X P [7 :0 ]
R X N
8:2 S/PDIF Input Multiplexer
General
The CS8416 employs a 8:2 S/PDIF input multiplexer to accommodate up to eight channels of input digital
audio data. Digital audio data may be single-ended or differential. Differential inputs utilize RXP[7:0] and
a shared RXN. Single ended signals are accommodated by using the RXP[7:0] inputs and AC coupling
RXN to ground.
All active inputs to the CS8416 8:2 input multiplexer should be coupled through a capacitor as these inputs
are biased at VL/2 when selected. These inputs are floating when not selected. Unused multiplexer inputs
should be left floating or tied to AGND. The recommended capacitor value is 0.01 μ F to 0.1 μ F. The rec-
ommended dielectrics for the AC coupling capacitors are C0G or X7R.
The input voltage range for the input multiplexer is set by the I/O power supply pin, VL. The input voltage
of the RXP[7:0] and RXN pins is also set by the level of VL. Input signals with voltage levels above VL or
below DGND may degrade performance or damage the part.
Software Mode
The multiplexer select line control is accessed through bits RXSEL[2:0] in control port register 04h. The
multiplexer defaults to RXP0.
V L = 5 .0 V : (1 5 0 0 + 8 0 0 /N ) Ω
V L = 3 .3 V : (1 5 0 0 + 1 5 0 0 /N ) Ω
If RXP[7:0] is selected by either the receiver MUX or the TX passthrough MUX, N=1.
If RXP[7:0] is selected by both the receiver MUX and the TX passthrough MUX, N=2.
If RXP[7:0] is not selected at all, N=0 (i.e. high impedance).
V L = 5 .0 V : 2 .3 k Ω
V L = 3 .3 V : 3 .0 k Ω
“External AES3/SPDIF/IEC60958 Receiver Components” on page
Figure 9. Receiver Input Structure
2 2 k Ω
2 2 k Ω
A G N D
V L
(2 2 0 0 0 /N ) Ω
(2 2 0 0 0 /N ) Ω
+
-
49.
Figure 9
CS8416
shows
27