DSPIC30F2010-20E/MM Microchip Technology, DSPIC30F2010-20E/MM Datasheet - Page 127

• Manufacturer Part Number: DSPIC30F2010-20E/MM
• Description: IC,DSP,16-BIT,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.3
The dsPIC30F2010 differentiates between various
kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Different registers are affected in different ways by var-
ious Reset conditions. Most registers are not affected
by a WDT wake-up, since this is viewed as the resump-
tion of normal operation. Status bits from the RCON
register are set or cleared differently in different Reset
situations, as indicated in
used in software to determine the nature of the Reset.
A block diagram of the on-chip Reset circuit is shown in
Figure 19-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
FIGURE 19-2:
© 2011 Microchip Technology Inc.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset cause by trap lockup (TRAPR)
Reset caused by illegal opcode, or by using an
uninitialized W register as an Address Pointer
(IOPUWR)
MCLR
V
DD
Illegal Opcode/
Uninitialized W Register
Reset
Instruction
RESET
Trap Conflict
Brown-out
V
Sleep or Idle
Module
Detect
DD
WDT
Reset
RESET SYSTEM BLOCK DIAGRAM
Rise
Table
BOREN
Glitch Filter
Digital
19-5. These bits are
POR
BOR
19.3.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally 1.85V. The device supply voltage character-
istics must meet specified starting voltage and rise rate
requirements. The POR pulse will Reset a POR timer
and place the device in the Reset state. The POR also
selects the device clock source identified by the
The POR circuit inserts a small delay, T
nominally 10 μs and ensures that the device bias cir-
cuits are stable. Furthermore, a user selected power-
up time-out (T
is based on device Configuration bits and can be 0 ms
(no delay), 4 ms, 16 ms, or 64 ms. The total delay is at
device power-up T
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock, and the PC will jump to
the Reset vector.
The timing for the SYSRST signal is shown in
Figure 19-3 through Figure 19-5.
oscillator configuration fuses.
DD
POR: POWER-ON RESET
rise is detected. The Reset pulse will occur
PWRT
dsPIC30F2010
POR
) is applied. The T
S
R
+ T
PWRT
Q
. When these delays
DS70118J-page 127
PWRT
POR
SYSRST
POR
), which is
parameter
, which is