DSPIC30F2010-20E/MM Microchip Technology, DSPIC30F2010-20E/MM Datasheet - Page 175
![IC,DSP,16-BIT,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC30F2010-20E/MM
Manufacturer Part Number
DSPIC30F2010-20E/MM
Description
IC,DSP,16-BIT,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F2010-20ISO.pdf
(202 pages)
3.DSPIC30F2010-20ISO.pdf
(6 pages)
4.DSPIC30F2010-20ISO.pdf
(26 pages)
Specifications of DSPIC30F2010-20E/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2010-20E/MM
Manufacturer:
Microchip Technology
Quantity:
135
- DSPIC30F2011-20IP PDF datasheet
- DSPIC30F2010-20ISO PDF datasheet #2
- DSPIC30F2010-20ISO PDF datasheet #3
- DSPIC30F2010-20ISO PDF datasheet #4
- Current page: 175 of 202
- Download datasheet (3Mb)
TABLE 22-35: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
© 2011 Microchip Technology Inc.
AC CHARACTERISTICS
SP70
SP71
SP72
SP73
SP30
SP31
SP35
SP40
SP41
SP50
SP51
SP52
SP60
Note 1:
Param
No.
2:
3:
4:
TssL2doV SDO
TscL
TscH
TscF
TscR
TdoF
TdoR
TscH2doV,
TscL2doV
TdiV2scH,
TdiV2scL
TscH2diL,
TscL2diL
TssL2scH,
TssL2scL
TssH2doZ SS↑ to SDO
TscH2ssH
TscL2ssH
Symbol
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and
are not tested.
The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPI pins.
SCK
SCK
SCK
SCK
SDO
SDO
SDO
SCK
Setup Time of SDI
to SCK
Hold Time of SDI
to SCK
SS
High-Impedance
SS
SS
X
X
X
↓ to SCK
X
X
X
X
X
X
X
X
↑ after SCK
X
Edge
Input Low Time
Input High Time
Input Fall Time
Input Rise Time
Edge
Data Output Fall Time
Data Output Rise Time
Data Output Valid after
Data Output Valid after
X
X
Characteristic
Edge
Edge
X
X
↓ or SCK
Output
(4)
X
X
X
Data Input
Edge
Data Input
(3)
(3)
(1)
X
↑ input
(3)
(3)
1.5 T
Standard Operating Conditions: 2.5V to 5.5V
(unless otherwise stated)
Operating temperature
Min
120
CY
30
30
20
20
10
—
—
—
—
—
—
+ 40
Typ
10
10
—
—
—
—
—
—
—
—
—
—
—
(2)
dsPIC30F2010
-40°C ≤ T
-40°C ≤ T
Max
25
25
30
50
50
—
—
—
—
—
—
—
—
A
A
≤ +85°C for Industrial
≤ +125°C for Extended
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS70118J-page 175
See Note 3
See Note 3
See parameter
DO32
See parameter
DO31
Conditions
—
—
—
—
—
—
—
—
—
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