DSPIC30F2010-20E/MM Microchip Technology, DSPIC30F2010-20E/MM Datasheet - Page 16
![IC,DSP,16-BIT,CMOS,LLCC,28PIN,PLASTIC](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC30F2010-20E/MM
Manufacturer Part Number
DSPIC30F2010-20E/MM
Description
IC,DSP,16-BIT,CMOS,LLCC,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F2010-20ISO.pdf
(202 pages)
3.DSPIC30F2010-20ISO.pdf
(6 pages)
4.DSPIC30F2010-20ISO.pdf
(26 pages)
Specifications of DSPIC30F2010-20E/MM
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2010-20E/MM
Manufacturer:
Microchip Technology
Quantity:
135
dsPIC30F2010
2.4.1
The 17 x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output
using a scaler to support either 1.31 fractional (Q31)
or 32-bit integer results. Unsigned operands are
zero-extended into the 17th bit of the multiplier input
value. Signed operands are sign-extended into the
17th bit of the multiplier input value. The output of
the 17 x 17-bit multiplier/scaler is a 33-bit value,
which is sign-extended to 40 bits. Integer data is
inherently represented as a signed two’s complement
value, where the MSB is defined as a sign bit.
Generally speaking, the range of an N-bit two’s
complement integer is -2
integer, the data range is -32768 (0x8000) to 32767
(0x7FFF), including ‘0’. For a 32-bit integer, the data
range
2,147,483,645 (0x7FFF FFFF).
When the multiplier is configured for fractional
multiplication, the data is represented as a two’s
complement fraction, where the MSB is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit two’s
complement fraction with this implied radix point is -1.0
to (1-2
-1.0 (0x8000) to 0.999969482 (0x7FFF), including ‘0’
and has a precision of 3.01518x10
mode, a 16x16 multiply operation generates a 1.31
product, which has a precision of 4.65661x10
The same multiplier is used to support the MCU multi-
ply instructions, which include integer 16-bit signed,
unsigned and mixed sign multiplies.
The MUL instruction may be directed to use byte or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
2.4.2
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
via the barrel shifter, prior to accumulation.
DS70118J-page 16
1-N
is
). For a 16-bit fraction, the Q15 data range is
MULTIPLIER
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
-2,147,483,648
source
N-1
and
to 2
N-1
(0x8000 0000)
post-accumulation
– 1. For a 16-bit
-5
. In Fractional
-10
.
to
2.4.2.1
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active low and the
other input is complemented. The adder/subtracter
generates overflow status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS
Register.
• Overflow from bit 39: this is a catastrophic
• Overflow into guard bits 32 through 39: this is a
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow status bits
described above, and the SATA/B (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
1.
2.
3.
4.
5.
6.
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the correspond-
ing overflow trap flag enable bit (OVATE, OVBTE) in
the INTCON1 register (refer to
rupts”) is set. This allows the user to take immediate
action, for example, to correct system gain.
overflow in which the sign of the accumulator is
destroyed.
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
OA:
ACCA overflowed into guard bits
OB:
ACCB overflowed into guard bits
SA:
ACCA saturated (bit 31 overflow and saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB:
ACCB saturated (bit 31 overflow and saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB:
Logical OR of OA and OB
SAB:
Logical OR of SA and SB
Adder/Subtracter, Overflow and
Saturation
© 2011 Microchip Technology Inc.
Section 5.0 “Inter-