LTC4253AIUF-ADJ Linear Technology, LTC4253AIUF-ADJ Datasheet - Page 11

• Manufacturer Part Number: LTC4253AIUF-ADJ
• Description: IC,Power Control/Management,CMOS,LLCC,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIUF-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: QFN EP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4mm
• Product Length (mm): 4mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

OPERATIO
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient cur-
rents from the power bus as they charge. The flow of
current damages the connector pins and glitches the
power bus, causing other boards in the system to reset.
The LTC4253A-ADJ is designed to turn on a circuit board
supply in a controlled manner, allowing insertion or re-
moval without glitches or connector damage.
Initial Start-Up
The LTC4253A-ADJ resides on a removable circuit board
and controls the path between the connector and load or
power conversion circuitry with an external MOSFET switch.
Both inrush control and short-circuit protection are pro-
vided by the MOSFET.
A detailed schematic is shown in Figure 1. – 48V and
– 48RTN receive power through the longest connector
pins and are the first to connect when the board is
inserted. The GATE pin holds the MOSFET off during this
time. UV/UVL/OV/OVL determines whether or not the
MOSFET should be turned on based upon internal high
accuracy thresholds and an external divider. UV/UVL/OV/
OVL does double duty by also monitoring whether or not
the connector is seated. The top of the divider detects
– 48V RTN
(LONG PIN)
RESET
(LONG PIN)
– 48V RTN
(SHORT PIN)
– 48V
(LONG PIN)
2.37k 1%
2.1k 1%
0.976k
U
20k
1%
1%
R4
R3
R2
R1
294k
1%
2.74k
1%
C1
10nF
R5
Figure 1. – 48V/2.5A Application with Operating Range from 43V to 82V
0.1µF
C
C
SQ
SS
33nF
C
0.68µF
T
UVL
UV
OVL
OV
SS
SQTIMER
TIMER
RESET
LTC4253A-ADJ
SEL
PWRGD1
PWRGD2
PWRGD3
V
V
SENSE
DRAIN
EE
IN
GATE
R
2.5k
15k(1/4W)/6
EN3
EN2
1µF
IN
C
IN
10nF
C
C
R
D
R6
5.6k
1M
R
10Ω
V
C
IN
†
Q1
IRF530S
– 48RTN by way of a short connector pin that is the last to
mate during the insertion sequence.
Interlock Conditions
A start-up sequence commences once these “interlock”
conditions are met:
1. The input voltage V
2. The voltage at UV > V
3. The voltage at OVL < V
4. The input voltage at RESET < 0.8V
5. The (SENSE – V
6. The voltage at SS is < 0.2V (20 • V
7. The voltage on the TIMER capacitor (C
8. The voltage at GATE is < 0.5V (V
The first four conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an overvoltage condition, the
TIMER pin voltage requirement is inhibited. Details are
described in the Applications Information, Timing Wave-
forms section.
R
0.02Ω
S
< 1V (V
R7
5.6k
EN2
†
V
†
IN
TMRL
R8
5.6k
)
†
+
EE
) voltage < 50mV (V
C
100µF
IN
POWER
MODULE 1
OUTPUT
L
UVHI
exceeds V
OVLO
LTC4253A-ADJ
MODULE 1
EN
POWER
EN3
LKO
GATEL
†
V
MOC207
†
IN
OS
(UVLO)
MODULE 2
EN
)
MODULE 2
POWER
OUTPUT
)
POWER
CB
T
) is
4253A F01
)
11
EN
MODULE 3
4253a-adjf
POWER