LTC4253AIUF-ADJ Linear Technology, LTC4253AIUF-ADJ Datasheet - Page 12

• Manufacturer Part Number: LTC4253AIUF-ADJ
• Description: IC,Power Control/Management,CMOS,LLCC,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIUF-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: QFN EP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4mm
• Product Length (mm): 4mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

OPERATIO
LTC4253A-ADJ
If RESET < 0.8V occurs after the LTC4253A-ADJ comes
out of UVLO (interlock condition 1) and undervoltage
(interlock condition 2), GATE and SS are released without
an initial TIMER cycle once the other interlock conditions
are met (see Figure 13a). If not, TIMER begins the start-up
sequence by sourcing 5µA into C
OV falls out of range or RESET asserts, the start-up cycle
stops and TIMER discharges C
until the aforementioned conditions are once again met. If
C
SS and GATE pins are released. GATE sources 50µA
(I
tance. The SS voltage ramp limits V
inrush current. The SEL pin selects between two different
modes of SS ramp-up (refer to Applications Information,
Soft-Start section). SQTIMER starts its ramp-up when
GATE is within 2.8V of V
This sets off the power good sequence in which PWRGD1,
PWRGD2 and then PWRGD3 is subsequently pulled low
after a delay, adjustable through the SQTIMER capacitor
C
external loads or power modules controlled by the three
PWRGD signals are turned on in a controlled manner
without overloading the power bus.
Two modes of operation are possible during the time the
MOSFET is first turned on, depending on the values of
external components, MOSFET characteristics and nomi-
nal design current. One possibility is that the MOSFET will
turn on gradually so that the inrush into the load capacitance
remains a low value. The output will simply ramp to – 48V
and the LTC4253A-ADJ will fully enhance the MOSFET. A
second possibility is that the load current exceeds the soft-
start current limit threshold of [V
case the LTC4253A-ADJ will ramp the output by sourcing
soft-start limited current into the load capacitance. If the
soft-start voltage is below 1.2V, the circuit breaker TIMER
is held low. Above 1.2V, TIMER ramps up. It is important
to set the timer delay so that, regardless of which start-up
mode is used, the TIMER ramp is less than one circuit
breaker delay time. If this condition is not met, the
LTC4253A-ADJ may shut down after one circuit breaker
delay time.
12
T
SQ
GATE
successfully charges to 4V, TIMER pulls low and both
or by external control inputs EN2 and EN3. In this way,
), charging the MOSFET gate and associated capaci-
U
IN
and DRAIN is lower than V
T
to less than 1V, then waits
SS
T
. If V
(t)/20 – V
SENSE
IN
, UVL/UV or OVL/
to control the
OS
]/R
S
. In this
DRNL
.
Board Removal
When the board is withdrawn from the card cage, the UVL/
UV/OVL/OV divider is the first to lose connection. This
shuts off the MOSFET and commutates the flow of current
in the connector. When the power pins subsequently
separate there is no arcing.
Current Control
Three levels of protection handle short-circuit and over-
load conditions. Load current is monitored by SENSE and
resistor R
50mV for a timed circuit breaker function; 60mV for an
analog current limit loop; and 200mV for a fast, feedforward
comparator which limits peak current in the event of a
catastrophic short-circuit.
If, due to an output overload, the voltage drop across R
exceeds 50mV, TIMER sources 200µA into C
ally charges to a 4V threshold and the LTC4253A-ADJ
shuts off. If the overload goes away before C
and SENSE measures less than 50mV, C
charges (5µA). In this way the LTC4253A-ADJ’s circuit
breaker function responds to low duty cycle overloads,
and accounts for the fast heating and slow cooling char-
acteristic of the MOSFET.
Higher overloads are handled by an analog current limit
loop. If the drop across R
limiting loop servos the MOSFET gate and maintains a
constant output current of V
V
and this increases MOSFET heating. If V
connecting an external resistor, R
DRAIN allows the fault timing cycle to be shortened by
accelerating the charging of the TIMER capacitor. The
TIMER pull-up current is increased by 8 • I
because SENSE > 50mV, TIMER charges C
time, and the LTC4253A-ADJ will eventually shut down.
Low impedance failures on the load side of the LTC4253A-
ADJ coupled with 48V or more driving potential can
produce current slew rates well in excess of 50A/µs. Under
these conditions, overshoot is inevitable. A fast SENSE
OUT
(MOSFET drain-source voltage drop) typically rises
S
. There are three distinct thresholds at SENSE:
ACL
S
reaches V
/R
S
. In current limit mode,
D
between V
ACL
OUT
DRN
T
, the current
T
T
T
. C
slowly dis-
reaches 4V
during this
. Note that
> V
T
OUT
eventu-
DRNCL
4253a-adjf
and
S
,