LTC4253AIUF-ADJ Linear Technology, LTC4253AIUF-ADJ Datasheet - Page 27

• Manufacturer Part Number: LTC4253AIUF-ADJ
• Description: IC,Power Control/Management,CMOS,LLCC,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIUF-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: QFN EP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4mm
• Product Length (mm): 4mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
Analog Current Limit and Fast Current Limit
In Figure 14a, when SENSE exceeds V
lated by the analog current limit amplifier loop. When
SENSE drops below V
Figure 14b, when a severe fault occurs, SENSE exceeds
V
current amplifier establishes control. If the severe fault
causes V
at V
by 8. This extra current is added to the TIMER pull-up
current of 200µA. This accelerated TIMER current of
(200µA + 8 • I
delay. Careful selection of C
prevent SOA damage in a low impedance fault condition.
Soft-Start
If SEL is floated high and the SS pin is not connected, this
pin defaults to a linear voltage ramp, from 0V to 1.4V in
about 200µs at GATE start-up, as shown in Figure 15a. If
a soft-start capacitor, C
PWRGD1
(12a) Momentary Circuit Breaker Fault
FCL
SENSE
TIMER
DRAIN
200µA + 8 • I
GATE
V
OUT
DRNCL
SS
and GATE immediately pulls down until the analog
OUT
CB FAULT
. I
1
DRN
DRN
to exceed V
2
DRN
flows into the DRAIN pin and is multiplied
V
V
V
TMRH
ACL
CB
) produces a shorter circuit breaker fault
U
ACL
Figure 12. Circuit Breaker Timing Behavior (All Waveforms are Referenced to V
SS
5µA
DRNCL
, is connected to this SS pin, the
, GATE is allowed to pull up. In
U
T
, the DRAIN pin is clamped
, R
D
W
and MOSFET helps
ACL
, GATE is regu-
U
PWRGD1
(12b) Circuit Breaker Time-Out
TIMER
SENSE
DRAIN
GATE
200µA + 8 • I
V
OUT
SS
V
TMRH
CB TIMES-OUT
1
CB FAULT
DRN
V
soft-start response is modified from a linear ramp to an
RC response (Equation 8), as shown in Figure 15b. This
feature allows load current to slowly ramp-up at GATE
start-up. Soft-start is initiated at time point 3 by a TIMER
transition from V
the OVL pin falling below the V
condition, or by the RESET pin falling < 0.8V after a Reset
condition. When the SS pin is below 0.2V, the analog
current limit amplifier keeps GATE low. Above 0.2V, GATE
is released and 50µA ramps up the compensation net-
work and GATE capacitance at time point 4. Meanwhile,
the SS pin voltage continues to ramp up. When GATE
reaches the MOSFET’s threshold, the MOSFET begins to
conduct. Due to the MOSFET’s high g
current quickly reaches the soft-start control value of
V
controlled by the current limit amplifier. The soft-start
control voltage reaches the circuit breaker voltage, V
time point 7 and the circuit breaker TIMER activates. As
the load capacitor nears full charge, load current begins
DRNCL
ACL
(t) (Equation 7). At time point 6, the GATE voltage is
2
V
V
ACL
CB
TMRH
to V
(12c) Multiple Circuit Breaker Fault
LTC4253A-ADJ
PWRGD1
TMRL
TIMER
SENSE
DRAIN
200µA + 8 • I
GATE
V
OUT
OVLO
SS
EE
V
(time points 1 and 2), by
TMRH
)
CB FAULT
threshold after an OV
1
DRN
2
m
CB TIMES-OUT
5µA
, the MOSFET
V
DRNCL
CB FAULT
3
27
4
4253a-adjf
V
V
ACL
CB
CB
4253A F12
at