LTC4253AIUF-ADJ Linear Technology, LTC4253AIUF-ADJ Datasheet - Page 8

• Manufacturer Part Number: LTC4253AIUF-ADJ
• Description: IC,Power Control/Management,CMOS,LLCC,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIUF-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: QFN EP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4mm
• Product Length (mm): 4mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

PI FU CTIO S
LTC4253A-ADJ
EN2 (Pin 1/Pin 18): Power Good Status Output Two
Enable. This is a TTL compatible input that is used to
control PWRGD2 and PWRGD3 outputs. When EN2 is
driven low, both PWRGD2 and PWRGD3 will go high.
When EN2 is driven high, PWRGD2 will go low provided
PWRGD1 has been active for more than one power good
sequence delay (t
EN2 can be used to control the power good sequence. This
pin is internally pulled low by a 120µA current source.
PWRGD2 (Pin 2/Pin 19): Power Good Status Output Two.
Power good sequence starts with DRAIN going below
2.39V and GATE is within 2.8V on V
active low after EN2 goes high and after one power good
sequence delay t
from the time PWRGD1 goes low, whichever comes later.
PWRGD2 is reset by PWRGD1 going high or EN2 going
low. This pin is internally pulled high by a 50µA current
source.
PWRGD1 (Pin 3/Pin 20): Power Good Status Output One.
At start-up, PWRGD1 latches active low one t
DRAIN is below 2.39V and GATE is within 2.8V of V
PWRGD1 status is reset by undervoltage, V
RESET going high or circuit breaker fault time-out. This
pin is internally pulled high by a 50µA current source.
V
to the positive side of the supply through a dropping
resistor. A shunt regulator clamps V
An internal undervoltage lockout (UVLO) circuit holds
GATE low until the V
overriding undervoltage and overvoltage events. If there is
no undervoltage, no overvoltage and V
UVLO, TIMER starts an initial timing cycle before initiating
GATE ramp up. If V
GATE pulls low immediately.
RESET (Pin 5/Pin 2): Circuit Breaker Reset Pin. This is an
asynchronous TTL compatible input. RESET going high
will pull GATE, SS, TIMER, SQTIMER low and the PWRGD
outputs high. The RESET pin has an internal glitch filter
that rejects any pulse < 20µs. After the reset of a latched
fault, the chip waits for the interlock conditions before
recovering as described in Interlock Conditions in the
Operation section.
8
IN
U
(Pin 4/Pin 1): Positive Supply Input. Connect this pin
U
SQT
SQT
IN
U
) provided by the sequencing timer.
provided by the sequencing timer
IN
drops below approximately 8.5V,
pin is greater than V
(SSOP/QFN)
IN
IN
. PWRGD2 will latch
at 13V above V
IN
comes out of
SQT
IN
LKO
after both
(UVLO),
(9V),
EE
IN
.
.
SS (Pin 6/Pin 3): Soft-Start Pin. This pin is used to ramp
inrush current during start up, thereby effecting control
over di/dt. A 20X attenuated version of the SS pin voltage
is presented to the current limit amplifier. This attenuated
voltage limits the MOSFET’s drain current through the
sense resistor during the soft-start current limiting. At the
beginning of the start-up cycle, the SS capacitor (C
ramped by a 28µA current source. The GATE pin is held
low until SS exceeds 20 • V
shunted by a 50k R
1.4V. This corresponds to an analog current limit SENSE
voltage of 60mV.
SEL (Pin 7/Pin 4): Soft-Start Mode Select. This is an
asynchronous TTL compatible input. SEL has an internal
pull-up of 20µA that will pull it high if it is floated. SEL
selects between two modes of SS ramp-up (see Applica-
tions Information, Soft-Start section).
SENSE (Pin 8/Pin 5): Circuit Breaker/Current Limit Sense
Pin. Load current is monitored by a sense resistor R
connected between SENSE and V
three steps. If SENSE exceeds V
breaker comparator activates a (200µA + 8 • I
pull-up current. If SENSE exceeds V
analog current-limit amplifier pulls GATE down to regulate
the MOSFET current at V
strophic short-circuit, SENSE may overshoot V
SENSE reaches V
parator pulls GATE low with a strong pull-down. To disable
the circuit breaker and current limit functions, connect
SENSE to V
V
Connect this pin to the negative side of the power supply.
GATE (Pin 11/Pin 8): N-channel MOSFET Gate Drive
Output. This pin is pulled high by a 50µA current source.
GATE is pulled low by invalid conditions at V
undervoltage, overvoltage, during the initial timing cycle,
a circuit breaker fault time-out or the RESET pin going
high. GATE is actively servoed to control the fault current
as measured at SENSE. Compensation capacitor, C
GATE stabilizes this loop. A comparator monitors GATE to
ensure that it is low before allowing an initial timing cycle,
then the GATE ramps up after an overvoltage event or
EE
(Pins 9, 10/Pin 7): Negative Supply Voltage Input.
EE
.
FCL
SS
(200mV), the fast current-limit com-
which limits the SS pin voltage to
ACL
/R
OS
S
. In the event of a cata-
= 0.2V. SS is internally
CB
EE
(50mV), the circuit
, and controlled in
ACL
(60mV), the
DRN
IN
(UVLO),
) TIMER
ACL
4253a-adjf
SS
C
) is
. If
, at
S