LTC4253AIUF-ADJ Linear Technology, LTC4253AIUF-ADJ Datasheet - Page 23

• Manufacturer Part Number: LTC4253AIUF-ADJ
• Description: IC,Power Control/Management,CMOS,LLCC,20PIN,PLASTIC
• Manufacturer: Linear Technology

Specifications of LTC4253AIUF-ADJ

• Family Name: LTC4253A-ADJ
• Package Type: QFN EP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4mm
• Product Length (mm): 4mm
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

APPLICATIO S I FOR ATIO
all conditions are met, initial timing starts and the TIMER
capacitor is charged by a 5µA current source pull-up. At
time point 3, TIMER reaches the V
initial timing cycle terminates. The TIMER capacitor is
quickly discharged. At time point 4, the V
reached and the conditions of GATE < V
and SS < 20 • V
up cycle begins. SS ramps up as dictated by R
in Equation 8); GATE is held low by the analog current limit
(ACL) amplifier until SS crosses 20 • V
GATE, 50µA sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current flows into the load ca-
pacitor at time point 5. At time point 6, load current
reaches SS control level and the analog current limit loop
activates. Between time points 6 and 8, the GATE voltage
is servoed, the SENSE voltage is regulated at V
(Equation 7) and soft-start limits the slew rate of the load
current. If the SENSE voltage (V
V
activates. The TIMER capacitor, C
(200µA + 8 • I
nears full charge, load current begins to decline. At time
point 8, the load current falls and the SENSE voltage drops
below V
the GATE pin ramps further. At time point 9, the SENSE
voltage drops below V
by a 5µA discharge cycle (cool-off). The duration between
time points 7 and 9 must be shorter than one circuit
breaker delay to avoid fault time-out during GATE ramp-
up. At time point B, GATE reaches its maximum voltage as
determined by V
V
pulls low at time point C after one t
setting off the second SQTIMER ramp up. Having satisfied
the requirement that PWRGD1 is low for more than one
t
threshold at time point D. This sets off the third SQTIMER
ramp-up. Having satisfied the requirement that PWRGD2
is low for more than one t
pulls high at time point E.
SQT
CB
GATEH
, PWRGD2 pulls low after EN2 pulls high above the V
threshold at time point 7, circuit breaker TIMER
and SQTIMER starts its ramp-up to 4V. PWRGD1
ACL
(t). The analog current limit loop shuts off and
DRN
OS
IN
must be satisfied before the GATE start-
) current pull-up. As the load capacitor
. At time point A, GATE ramps past
U
CB
SQT
, the fault TIMER ends, followed
U
, PWRGD3 pulls low after EN3
SENSE
TMRH
SQT
W
T
GATEL
OS
– V
from time point A,
is charged by a
threshold and the
TMRL
. Upon releasing
EE
, SENSE < V
) reaches the
threshold is
SS
U
• C
SS
ACL
(as
(t)
CB
IH
Live Insertion with Short Pin Control of UV/OV
In the example shown in Figure 9, power is delivered through
long connector pins whereas the UV/OV divider makes
contact through a short pin. This ensures the power con-
nections are firmly established before the LTC4253A-ADJ
is activated. At time point 1, the power pins make contact
and V
divider makes contact and UV > V
ternal logic checks for OV < V
V
When all conditions are met, initial timing starts and the
TIMER capacitor is charged by a 5µA current source pull-
up. At time point 3, TIMER reaches the V
and the initial timing cycle terminates. The TIMER capaci-
tor is quickly discharged. At time point 4, the V
old is reached and the conditions of GATE < V
SENSE < V
the GATE start-up cycle begins. SS ramps up as dictated
by R
amplifier until SS crosses 20 • V
50µA sources into the external MOSFET gate and compen-
sation network. When the GATE voltage reaches the
MOSFET’s threshold, current begins flowing into the load
capacitor at time point 5. At time point 6, load current
reaches SS control level and the analog current limit loop
activates. Between time points 6 and 8, the GATE voltage
is servoed and the SENSE voltage is regulated at V
and soft-start limits the slew rate of the load current. If the
SENSE voltage (V
at time point 7, the circuit breaker TIMER activates. The
TIMER capacitor, C
current pull-up. As the load capacitor nears full charge, load
current begins to decline. At point 8, the load current falls
and the SENSE voltage drops below V
current limit loop shuts off and the GATE pin ramps fur-
ther. At time point 9, the SENSE voltage drops below V
and the fault TIMER ends, followed by a 5µA discharge
current source (cool-off). When GATE ramps past V
threshold at time point A, SQTIMER starts its ramp-up.
PWRGD1 pulls low at time point C after one t
GATEL
SS
IN
, SENSE < V
• C
ramps through V
SS
CB
; GATE is held low by the analog current limit
and SS < 20 • V
SENSE
CB
T
, SS < 20 • V
is charged by a (200µA + 8 • I
– V
LKO
LTC4253A-ADJ
EE
. At time point 2, the UV/OV
OVHI
) reaches the V
OS
OS
must be satisfied before
OS
UVHI
, RESET < 0.8V, GATE <
. Upon releasing GATE,
and TIMER < V
. In addition, the in-
ACL
TMRH
(t). The analog
SQT
TMRL
CB
from time
threshold
threshold
23
thresh-
GATEL
4253a-adjf
ACL
GATEH
TMRL
DRN
(t)
CB
)
.
,