SI7900AEDN-T1-E3 Vishay, SI7900AEDN-T1-E3 Datasheet - Page 8

• Manufacturer Part Number: SI7900AEDN-T1-E3
• Description: MOSFET DUAL N-CH 20V 1212-8
• Manufacturer: Vishay
• Series: TrenchFET®r

Specifications of SI7900AEDN-T1-E3

• Fet Type: 2 N-Channel (Dual)
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 26 mOhm @ 8.5A, 4.5V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 6A
• Vgs(th) (max) @ Id: 900mV @ 250µA
• Gate Charge (qg) @ Vgs: 16nC @ 4.5V
• Power - Max: 1.5W
• Mounting Type: Surface Mount
• Package / Case: PowerPAK® 1212-8 Dual
• Transistor Polarity: N Channel
• Continuous Drain Current Id: 8.5A
• Drain Source Voltage Vds: 20V
• On Resistance Rds(on): 36mohm
• Rds(on) Test Voltage Vgs: 12V
• Threshold Voltage Vgs Typ: 900mV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SI7900AEDN-T1-E3TR

AN822
Vishay Siliconix
PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in
ment in thermal performance.
REFLOW SOLDERING
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
www.vishay.com
2
3° C/s (max)
140 - 170 °C
2
of will yield little improve-
Figure 3. Solder Reflow Temperatures and Time Durations
Maximum peak temperature at 240 °C is allowed.
Pre-Heating Zone
60 s (min)
3 ° C/s (max)
210 - 220 °C
ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
(Pb)-free solder profile, see http://www.vishay.com/
doc?73257.
Ramp-Up Rate
Time at Maximum Temperature
Temperature at 155 ± 15 °C
Temperature Above 180 °C
Maximum Temperature
Ramp-Down Rate
Figure 2. Solder Reflow Temperature Profile
Reflow Zone
50 s (max)
10 s (max)
183 °C
4 ° C/s (max)
+ 6 °C /Second Maximum
120 Seconds Maximum
70 - 180 Seconds
240 + 5/- 0 °C
20 - 40 Seconds
+ 6 °C/Second Maximum
Document Number 71681
03-Mar-06