DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 49

• Manufacturer Part Number: DS3104GN
• Description: Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
• Manufacturer: Maxim Integrated Products

the data on SDO, increment its address counter, and prefetch the following byte. After the address counter reaches
3FFFh, it rolls over to address 0000h and continues to increment.
Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by
pulling CS high. In response to early terminations, the DS3104-SE resets its SPI interface logic and waits for the
start of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a
data byte, the data byte is not written.
Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the
DS3104-SE is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support
this option, the bus master must not drive the SDI/SDO line when the DS3104-SE is transmitting.
AC Timing. See
Figure 7-5. SPI Clock Phase Options
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
SDI/SDO
SCLK
SCLK
SCLK
SCLK
Table 10-10
CS
CPOL = 0, CPHA = 0
CPOL = 0, CPHA = 1
CPOL = 1, CPHA = 0
CPOL = 1, CPHA = 1
and
Figure 10-4
MSB
CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES)
6
for AC timing specifications for the SPI interface.
5
4
3
2
1
LSB
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