DS3104GN Maxim Integrated Products, DS3104GN Datasheet - Page 78
DS3104GN
Manufacturer Part Number
DS3104GN
Description
Timers & Support Products SDH-SONET-Synchronou s Ethernet Line Card
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3104GN.pdf
(136 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Digital Alternate Frequency (DIG2AF). Selects alternative frequencies.
Bit 6: Digital2 SONET or SDH Frequencies (DIG2SS). This bit specifies whether the clock rates generated by the
Digital2 clock synthesizer are multiples of 1.544MHz (SONET compatible) or multiples of 2.048MHz (SDH
compatible) or alternate frequencies. The specific multiple is set in the DIG2F field of the
RST = 0 the default value of this bit is latched from the SONSDH pin.
Bit 5: Digital1 SONET or SDH Frequencies (DIG1SS). This bit specifies whether the clock rates generated by the
Digital1 clock synthesizer are multiples of 1544kHz (SONET compatible) or multiples of 2048kHz (SDH
compatible). The specific multiple is set in the DIG1F field of the
this bit is latched from the SONSDH pin.
19-4627; Rev 7; 8/10
________________________________________________________________________________________ DS3104-SE
0 = Digital2 N x E1 or N x DS1 frequency specified by DIG2SS and MCR7:DIG2F.
1 = Digital2 6.312MHz, 10MHz, or N x 19.44MHz frequency specified by DIG2SS and MCR7:DIG2F.
DIG2AF = 0:
DIG2AF = 1:
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
6.312MHz, 10MHz, or N x 19.44MHz
DIG2AF
7
0
see below
DIG2SS
6
MCR6
Master Configuration Register 6
38h
see below
DIG1SS
5
—
4
1
MCR7
—
3
1
register. When RST = 0 the default value of
—
2
1
MCR7
—
1
1
register. When
78 of 136
—
0
1
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