ispPAC-CLK5316S-01TN64I Lattice, ispPAC-CLK5316S-01TN64I Datasheet
ispPAC-CLK5316S-01TN64I
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ispPAC-CLK5316S-01TN64I Summary of contents
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... REFSEL FBK © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor General Description The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications. The ispClock5312S, the first member of the ispClock5300S family, provides single-ended ultra low skew outputs. Each pair of outputs may be independently configured to support separate I/O standards (LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen- dent programmable control of termination, slew-rate, and timing skew. All confi ...
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... Lattice Semiconductor Figure 2. ispClock5308S Functional Block Diagram VTT_REFA VTT_REFB REFA_REFP + REFB_REFN 0 1 REFSEL FBK VTT_FBK Figure 3. ispClock5312S Functional Block Diagram VTT_REFA VTT_REFB REFA_REFP + REFB_REFN 0 1 REFSEL FBK VTT_FBK ispClock5300S Family Data Sheet RESET OEX LOCK OUTPUT ENABLE DETECT CONTROLS OUTPUT DIVIDERS ...
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... Lattice Semiconductor Figure 4. ispClock5316S Functional Block Diagram VTT_REFA VTT_REFB REFA_REFP REFB_REFN 0 1 REFSEL FBK VTT_FBK Figure 5. ispClock5320S Functional Block Diagram VTT_REFA VTT_REFB REFA_REFP REFB_REFN 0 1 REFSEL FBK VTT_FBK RESET OEX LOCK OUTPUT ENABLE DETECT CONTROLS OUTPUT DIVIDERS PHASE LOOP 5-bit VCO ...
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... Lattice Semiconductor Absolute Maximum Ratings Core Supply Voltage -0.5 to 5.5V CCD PLL Supply Voltage -0.5 to 5.5V CCA JTAG Supply Voltage -0.5 to 5.5V CCJ Output Driver Supply Voltage V CCO Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V 1 Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130° ...
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... Lattice Semiconductor 2 E CMOS Memory Write/Erase Characteristics Parameter Erase/Reprogram Cycles Performance Characteristics – Power Supply Symbol Parameter 2 I Core Supply Current CCD Incremental I per Active CCD I CCDADDER Output 2 I Analog Supply Current CCA Output Driver Supply Current I CCO (per Bank) I JTAG I/O Supply Current (static) CCJ 1 ...
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... Lattice Semiconductor Electrical Characteristics – Differential SSTL18 Symbol Parameter V Low-Logic Level Input Voltage Logic Level Input Voltage IH Input Pair Differential Crosspoint V IX Voltage Electrical Characteristics – Differential SSTL2 Symbol Parameter V DC Differential Input Voltage Swing SWING(DC Input Differential Voltage SWING(AC) Input Pair Differential Crosspoint ...
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... Lattice Semiconductor DC Electrical Characteristics – Input/Output Loading Symbol Parameter I Input Leakage LK I Input Pull-up Current PU I Input Pull-down Current PD I Tristate Leakage Output OLK C Input Capacitance IN 1. Applies to clock reference inputs when termination ‘open’. 2. Applies to TDI, TMS and RESET inputs. ...
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... Lattice Semiconductor Output Rise and Fall Times – Typical Values Slew 1 (Fastest) Output Type LVTTL 0.54 0.76 LVCMOS 1.8V 0.75 0.69 LVCMOS 2.5V 0.57 0.69 LVCMOS 3.3V 0.55 0.77 SSTL18 0.55 0.40 SSTL2 0.50 0.40 SSTL3 0.50 0.45 HSTL 0.60 0.45 eHSTL 0 ...
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... Lattice Semiconductor Programmable Input and Output Termination Characteristics Symbol Parameter R Input Resistance IN R Output Resistance OUT Output Resistor R OUT_TEMPCO Temperature Coefficient ispClock5300S Family Data Sheet Conditions Min. Rin=40Ω setting 36 Rin=45Ω setting 40.5 Rin=50Ω setting 45 Rin=55Ω setting 49.5 Rin=60Ω ...
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... Lattice Semiconductor Performance Characteristics – PLL Symbol Parameter Reference and feedback input f f REF, FBK frequency range t Reference and feedback input CLOCKHI, t clock HIGH and LOW times CLOCKLO t Reference and feedback input RINP, t rise and fall times FINP Phase detector input frequency ...
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... Lattice Semiconductor Timing Specifications Skew Matching Symbol Parameter t Output-output Skew SKEW Programmable Skew Control Symbol Parameter t Skew Control Range SKRANGE SK Skew Steps per Range STEPS 2 t Skew Step Size SKSTEP 3 t Skew Time Error SKERR 1. Skew control range is a function of VCO frequency (f ...
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... Lattice Semiconductor Static Phase Offset vs. Reference Clock Logic Type Reference Clock Logic Symbol (REFA/REFB) LVCMOS 33 LVCMOS 25 LVCMOS 18 SSTL3 t φ – Static Phase Offset SSTL2 ( ) HSTL(1.5V) eHSTL(1.8V) LVDS (2.5V) 1 LVPECL 1. The output clock to feedback can be skewed to center the static phase offset spread. ...
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... Lattice Semiconductor JTAG Interface and Programming Mode Symbol Parameter f Maximum TCK Clock Frequency MAX t TCK Clock Pulse Width, High CKH t TCK Clock Pulse Width, Low CKL t Program Enable Delay Time ISPEN t Program Disable Delay Time ISPDIS t High Voltage Discharge Time, Program ...
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... Lattice Semiconductor Timing Diagrams Figure 8. Erase (User Erase or Erase All) Timing Diagram VIH TMS VIL SU1 SU1 CKH CKL VIH TCK VIL State Update-IR Run-Test/Idle (Erase) Figure 9. Programming Timing Diagram VIH TMS VIL SU1 H t CKH VIH TCK VIL State Update-IR Figure 10 ...
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... Lattice Semiconductor Typical Performance Characteristics I vs. f CCD VCO (Normalized to 400MHz) 1.2 1.0 0.8 0.6 0.4 0.2 0 150 200 250 f (MHz) VCO Period Jitter vs. Input/Output Frequency 80 60 V=16 40 V=8 20 V=4 V 100 150 Input/Output Frequency (MHz) Phase Jitter vs. Input/Output Frequency 100 80 V=16 60 V=8 ...
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... Lattice Semiconductor Detailed Description PLL Subsystem The ispClock5300S provides an integral phase-locked-loop (PLL) which may be used to generate output clock sig- nals at lower, higher, or the same frequency as a user-supplied input reference signal. The core functions of the PLL are an edge-sensitive phase detector, a programmable loop filter, and a high-speed voltage-controlled oscilla- tor (VCO) ...
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... Lattice Semiconductor Figure 12. PLL Loop Bandwidth vs. Feedback Divider Setting (Nominal) PLL Bandwidth vs. VCO Frequency and V-Divider (Standard Mode) 6.0 5.0 Vdiv=1 4.0 3.0 2.0 1.0 0.0 100 200 300 VCO Frequency (MHz) Dynamic Phase Offset vs. Input Frequency and Modulation Index (MI) ...
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... Lattice Semiconductor When the PLL is selected (PLL_BYPASS=LOW) and locked, the output frequency of each V divider (f culated as: where f is the frequency of V divider the input reference frequency ref V is the setting of the V divider used to close the PLL feedback path fbk V is the output divider K ...
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... Lattice Semiconductor • eHSTL • Differential SSTL1.8 • Differential SSTL2 • Differential SSTL3 • Differential HSTL • LVDS • LVPECL (differential, 3.3V) Figure 13. Reference and Feedback Input REFA_REFP REFB_REFN REFSEL FBK VTT_FBK Each input features internal programmable termination resistors as shown in Figure 14. The REFA and REFB inputs terminate to VTT_REFA and VTT_REFB respectively ...
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... Lattice Semiconductor Figure 14. Input Receiver Termination Configuration REFA_REFP REFB_REFN Feedback input is terminated to the VTT_FBK pin through a programmable resistor. The following usage guidelines are suggested for interfacing to supported logic families. Differential Receiver + – Single-ended Receiver R T VTT_REFA R T Single-ended Receiver VTT_REFB ...
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... Lattice Semiconductor LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V) The receiver should be set to LVCMOS or LVTTL mode, and the input signal can be connected to either the REFA or REFB pins. CMOS transmission lines are generally source terminated, so all termination resistors should be set to the OPEN state. Figure 15 shows the proper configuration. Please note that because switching thresholds are different for LVCMOS running at 1.8V, there is a separate confi ...
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... Lattice Semiconductor Figure 17. LVDS Input Receiver Configuration LVDS Driver Note that while a floating 100Ω resistor forms a complete termination for an LVDS signal line, additional circuitry may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out- put driver typically requires an external DC ‘pull-down’ path properly bias its open emitter output stage ...
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... Lattice Semiconductor actual impedance required will be a function of the driver used to generate the signal and the transmission medium used (PCB traces, connectors and cabling). The ispClock5300S’s ability to adjust input impedance over a range of 40Ω to 70Ω allows the user to adapt his circuit to non-ideal behaviors from the rest of the system without having to swap out components ...
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... Lattice Semiconductor Each of the ispClock5300S’s output driver banks can be configured to support the following logic outputs: • LVTTL • LVCMOS (1.8V, 2.5V, 3.3V) • SSTL2 • SSTL3 • HSTL • eHSTL To provide LVTTL, LVCMOS, SSTL2, SSTL3, HSTL and eHSTL outputs, the CMOS output drivers in each bank are enabled. These circuits provide logic outputs which swing from ground to the VCCO supply rail. The choice of VCCO to be supplied to a given bank is determined by the logic standard to which that bank is confi ...
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... Lattice Semiconductor Figure 21. Configuration for SSTL2, SSTL3, and HSTL Output Modes ispClock5300S SSTL/HSTL/eHSTL Mode (SSTL) 20 (HSTL, eHSTL) ispClock5300S Configurations The ispClock5300S device can be configured to operate in four modes. They are: • Zero Delay Buffer Mode • Mixed Zero Delay and Non-Zero Delay Buffer Mode • ...
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... Lattice Semiconductor Figure 22. ispClock5300S configured as Zero Delay Buffer Mode ispClock5300S Single Ended / Differential Clock Input Mixed Zero Delay and Non-Zero Delay Buffer Mode Figure 23 shows the operation of the ispClock5300S in Mixed Zero Delay and Non Zero Delay modes. In this mode the output switch matrix is configured to route non selected reference clock, selected reference clock, and the zero delay clock through the PLL ...
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... Lattice Semiconductor Figure 23. Mixed Zero Delay and Non Zero Delay Buffer Mode Single Ended / Clock Input Single Ended / Clock Input ispClock5300S V1 PLL V2 V3 Internal Feedback External Feedback 28 ispClock5300S Family Data Sheet ...
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... Lattice Semiconductor Non Zero Delay Buffer Mode 1 In the non zero delay buffer mode as shown in Figure 24 the output routing matrix completely bypasses the PLL. Each of the single ended input reference clocks can be routed to any number of available output clocks. In this mode of operation there is no skew control. ...
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... In applications where a majority of the ispClock5300S’s outputs are active and operating at or near maximum out- put frequency, package thermal limitations may need to be considered to ensure a successful design. Thermal characteristics of the packages employed by Lattice Semiconductor may be found in the document Thermal Man- agement which may be obtained at www.latticesemi.com. ...
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... Lattice Semiconductor Figure 25. Maximum Ambient Temperature vs. Number of Active Output Banks Temperature Derating Curves Outputs LVCMOS33, 3.3V, f (ispClock 5304S, 5308S, 5312S Number of Active Banks Note that because of variations in circuit board mounting, construction, and layout, as well as convective and forced airflow present in a given design, actual die operating temperature is subject to considerable variation from that which may be theoretically predicted from package characteristics and device power dissipation ...
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... Lattice Semiconductor (f = 400MHz) to 780ps (f VCO VCO coarse skew mode is selected, an additional divide-by-2 stage is effectively inserted between the VCO and the V- divider bank, as shown in Figure 26. When assigning divider settings in coarse skew mode, one must account for this additional divide-by-two so that the VCO still operates within its specified range (160-400MHz). ...
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... Lattice Semiconductor outputs in Figure 27 show how the various sources of skew error stack up in this case. Note that if two or more out- puts are programmed to the same skew setting, then the contribution of the t When outputs are configured or loaded differently, this also has an effect on skew matching output is set to support a different logic type, this can be accounted for by using the t(ioo) output adders specifi ...
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... If the RESET pin is not driven by an external logic it should be pulled Software-Based Design Environment Designers can configure the ispClock5300S using Lattice’s PAC-Designer software, an easy to use, Microsoft Win- dows compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer envi- ronment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to the serial programming interface pins of the ispClock5300S. A library of confi ...
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... Lattice Semiconductor Figure 30. PAC-Designer Design Entry Screen In-System Programming The ispClock5300S is an In-System Programmable (ISP™) device. This is accomplished by integrating all 2 E CMOS configuration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored ...
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... Evaluation Fixture Included in the basic ispClock5300S Design Kit is an engineering prototype board that can be connected to the parallel port using a Lattice ispDOWNLOAD ispClock5300S and can be used in real time to check circuit operation as part of the design process. Input and out- put connections (SMA connectors for all RF signals) are provided to aid in the evaluation of the ispClock5300S for a given application ...
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... Lattice Semiconductor Figure 32. ispClock5300S TAP Registers TDI TAP Controller Specifics The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a small 16-state controller design ...
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... Lattice Semiconductor Figure 33. TAP States Test-Logic-Rst Run-Test/Idle Note: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state and move to the desired state ...
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... The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111). The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The bit code for this instruction is defined by Lattice as shown in Table 4. The EXTEST (external test) instruction is required and will place the device into an external boundary test mode while also enabling the boundary scan register to be connected between TDI and TDO. The bit code of this instruc- tion is defi ...
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... MSB XXXX / 0000 0001 0111 1000 / 0000 0100 001 / 1 JEDEC Manufacturer Part Number Identity Code for (16 bits) Lattice Semiconductor 0178h = ispClock5316S (11 bits) (3.3V version) MSB XXXX / 0000 0001 0111 0110 / 0000 0100 001 / 1 JEDEC Manufacturer Part Number ...
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... Lattice Semiconductor In addition to the four instructions described above, there are 20 unique instructions specified by Lattice for the ispClock5300S. These instructions are primarily used to interface to the various user registers and the E non-volatile memory. Additional instructions are used to control or monitor other features of the device, including boundary scan operations ...
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... Lattice Semiconductor Pin Descriptions – ispClock5304S, 5308S, 5312S Pin Name Description VCCO_0 Output Driver ‘0’ VCC VCCO_1 Output Driver ‘1’ VCC VCCO_2 Output Driver ‘2’ VCC VCCO_3 Output Driver ‘3’ VCC VCCO_4 Output Driver ‘4’ VCC VCCO_5 Output Driver ‘ ...
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... Lattice Semiconductor Pin Descriptions – ispClock5304S, 5308S, 5312S (Continued) Pin Name Description LOCK PLL Lock indicator, HIGH indicates PLL lock OEX Output Enable X OEY Output Enable Y PLL_BYPASS PLL Bypass RESET Reset PLL NC No internal connection 1. Internal pull-down resistor. 2. Internal pull-up resistor. ...
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... Lattice Semiconductor Pin Descriptions – ispClock5316S, 5320S Pin Name VCC_0 Output Driver ‘0’ VCC VCC_1 Output Driver ‘1’ VCC VCC_2 Output Driver ‘2’ VCC VCC_3 Output Driver ‘3’ VCC VCC_4 Output Driver ‘4’ VCC VCC_5 Output Driver ‘5’ VCC VCC_6 Output Driver ‘ ...
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... Lattice Semiconductor Pin Descriptions – ispClock5316S, 5320S (Continued) Pin Name GNDD Digital GND REFA_REFP Clock Reference A/ Positive Differential Input REFB_REFN Clock Reference B/ Negative Differential Input REFSEL Clock Reference Select input (LVCMOS) VTT_REFA Termination voltage for reference input A FBK Feedback input VTT_FBK ...
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... Lattice Semiconductor Detailed Pin Descriptions VCCO_[0..9], GNDO_[0..9] – These pins provide power and ground for each of the output banks. In the case when an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should be tied to ground. ALL GNDO pins should be tied to ground regardless of whether the associated bank is used or not. When a bank is used, it should be individually bypassed with a capacitor in the range of 0.01 to 0.1µ ...
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... Lattice Semiconductor Package Diagrams 48-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR 0. SECTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND DETERMINED AT DATUM PLANE DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 AND E1 DIMENSIONS ...
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... Lattice Semiconductor 64-Pin TQFP (Dimensions in Millimeters) PIN 1 INDICATOR TOP VIEW SIDE VIEW b SEATING PLANE 0. A-B D 64X SECTION B-B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982. 2. ALL DIMENSIONS ARE IN MILLIMETERS. DATUMS A, B AND DETERMINED AT DATUM PLANE DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ...
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... Lattice Semiconductor Part Number Description ispPAC-CLK53XXS - 01 XXXX X Device Family Device Number CLK5304S CLK5308S CLK5312S CLK5316S CLK5320S Ordering Information Conventional Packaging Part Number ispPAC-CLK5320S-01T64C ispPAC-CLK5316S-01T64C ispPAC-CLK5312S-01T48C ispPAC-CLK5308S-01T48C ispPAC-CLK5304S-01T48C Part Number ispPAC-CLK5320S-01T64I ispPAC-CLK5316S-01T64I ispPAC-CLK5312S-01T48I ispPAC-CLK5308S-01T48I ispPAC-CLK5304S-01T48I Lead-Free Packaging Part Number ispPAC-CLK5320S-01TN64C ispPAC-CLK5316S-01TN64C ispPAC-CLK5312S-01TN48C ...
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... Lattice Semiconductor Lead-Free Packaging (Cont.) Part Number ispPAC-CLK5320S-01TN64I ispPAC-CLK5316S-01TN64I ispPAC-CLK5312S-01TN48I ispPAC-CLK5308S-01TN48I ispPAC-CLK5304S-01TN48I Industrial Clock Outputs Supply Voltage 20 3.3V 16 3.3V 12 3.3V 8 3.3V 4 3.3V 50 ispClock5300S Family Data Sheet Package Pins Lead-Free TQFP 64 Lead-Free TQFP 64 Lead-Free TQFP 48 Lead-Free TQFP 48 Lead-Free TQFP 48 ...
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... Lattice Semiconductor Package Options ispClock5304S: 48-pin TQFP VCCO_0 BANK_0A GND_0 BANK_0B ispClock5300S Family Data Sheet ispPAC-CLK5304S-01T48C VCCO_1 31 BANK_1A 30 GNDO_1 29 BANK_1B ...
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... Lattice Semiconductor ispClock5308S: 48-pin TQFP VCCO_0 BANK_0A GNDO_0 BANK_0B VCCO_1 BANK_1A GNDO_1 BANK_1B ispClock5300S Family Data Sheet ispPAC-CLK5308S-01T48C VCCO_3 31 BANK_3A 30 GNDO_3 29 BANK_3B 28 VCCO_2 27 BANK_2A 26 GNDO_2 25 BANK_2B ...
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... Lattice Semiconductor ispClock5312S: 48-pin TQFP VCCO_0 BANK_0A GNDO_0 BANK_0B VCCO_1 BANK_1A GNDO_1 BANK_1B VCCO_2 BANK_2A GNDO_2 BANK_2B ispClock5300S Family Data Sheet ispPAC-CLK5312S-01T48C VCCO_5 35 BANK_5A 34 GNDO_5 33 BANK_5B 32 VCCO_4 31 BANK_4A 30 GNDO_4 29 BANK_4B 28 VCCO_3 27 BANK_3A 26 GNDO_3 25 BANK_3B ...
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... Lattice Semiconductor ispClock5316S: 64-pin TQFP BANK_0A BANK_0B VCCO_1 BANK_1A BANK_1B GNDO_1 VCCO_2 BANK_2A BANK_2B GNDO_2 VCCO_3 BANK_3A BANK_3B GNDO_3 ispPAC-CLK5316S-01T64C ispClock5300S Family Data Sheet 48 BANK_7A 47 BANK_7B 46 VCCO_6 45 BANK_6A 44 BANK_6B 43 GNDO_6 42 VCCO_5 41 BANK_5A 40 BANK_5B 39 GNDO_5 38 VCCO_4 37 BANK_4A 36 BANK_4B 35 GNDO_4 ...
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... Lattice Semiconductor ispClock5320S: 64-pin TQFP BANK_0A BANK_0B VCCO_1 BANK_1A BANK_1B GNDO_1 VCCO_2 BANK_2A BANK_2B GNDO_2 VCCO_3 BANK_3A BANK_3B GNDO_3 BANK_4A BANK_4B ispPAC-CLK5320S-01T64C ispClock5300S Family Data Sheet 48 BANK_9A 47 BANK_9B 46 VCCO_8 45 BANK_8A 44 BANK_8B 43 GNDO_8 42 VCCO_7 41 BANK_7A 40 BANK_7B 39 GNDO_7 38 VCCO_6 37 BANK_6A 36 BANK_6B 35 GNDO_6 34 BANK_5A ...
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... Lattice Semiconductor Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-408-826-6002 (Outside North America) e-mail: isppacs@latticesemi.com Internet: www.latticesemi.com Revision History Date Version April 2006 01.0 May 2006 01.1 June 2006 01.2 October 2006 01.3 October 2007 01.4 Change Summary Initial release. Performance Characteristics-PLL table - Correction to min. output frequency, f Skew Mode ...