LX128V-32FN208C Lattice, LX128V-32FN208C Datasheet - Page 14
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LX128V-32FN208C
Manufacturer Part Number
LX128V-32FN208C
Description
Analog & Digital Crosspoint ICs 128 I/O Switch Matrix, 3.3V, SERDES, 3.2ns, Pb-Free
Manufacturer
Lattice
Datasheet
1.LX256EV-5FN484C.pdf
(75 pages)
Specifications of LX128V-32FN208C
Maximum Dual Supply Voltage
3.6 V
Minimum Dual Supply Voltage
3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
3.3 V
Supply Type
Triple
Configuration
128 x 128
Package / Case
FPBGA-208
Data Rate
21 Gbps
Input Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Output Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LX128V-32FN208C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 7. I/O Pin Connection to the sysCLOCK PLL
GCLK_IN
1. Some pins are shared. See Logic Signal Connections Table for details.
GCLK_IN
Input Clock
(M) Divider
÷ 1 to 32
PLL_RST
--------------------
Programmable
Programmable
Divider (N)
Feedback
x 1 to 32
+ Delay
- Delay
PLL_FBK
PLL (n)
Post-scalar
(V) Divider
(K) Divider
1, 2, 4, 8,
2, 4, 8,
16, 32
16, 32
Clock
÷
÷
To Adjacent_PLL
From Adjacent_PLL
Clock Net
PLL_LOCK
1
CLK_OUT
11
GRP
Resetb (0)
(from selected blocks)
Control Array
ispGDX2 Family Data Sheet
GDX Block
Output
Latch
Input
Reg/
Latch
Reg/
Delay