LX128V-32FN208C Lattice, LX128V-32FN208C Datasheet - Page 68

• Manufacturer Part Number: LX128V-32FN208C
• Description: Analog & Digital Crosspoint ICs 128 I/O Switch Matrix, 3.3V, SERDES, 3.2ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX128V-32FN208C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispGDX2-256 Logic Signal Connections (Continued)
GND
BK5_IO28
BK5_IO29
BK5_IO30
BK5_IO31/
CLK_OUT0
SEL0
SEL1
GCLK/CE1
BK6_IO0/
CLK_OUT1
GND
BK6_IO4
BK6_IO9
BK6_IO10
BK6_IO11
GND
BK6_IO12
BK6_IO13
BK6_IO14
BK6_IO15
BK6_IO16
BK6_IO17
BK6_IO18
BK6_IO19
GND
BK6_IO20/
PLL_FB1
BK6_IO21/
VREF6
BK6_IO22
BK6_IO23
BK6_IO31
GCLK/CE0
BK6_IO1
BK6_IO2
BK6_IO3
BK6_IO5
BK6_IO6
BK6_IO7
BK6_IO8
BK6_IO24
BK6_IO25
BK6_IO26
BK6_IO27
BK6_IO28
BK6_IO29
BK6_IO30
Signal
Name
sysIO
Bank
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
Pair/Polarity
CLK0P
CLK0N
LVDS
100N
100P
101N
101P
102N
102P
103N
103P
104N
104P
105N
105P
106N
106P
107N
107P
108N
108P
109N
109P
110N
110P
111N
111P
94P
94N
95P
95N
96N
96P
97N
97P
98N
98P
99N
99P
-
-
-
-
-
-
Block MRB
GDX
7A
7A
6A
6A
6A
5B
5B
5B
5B
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
7A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
-
-
-
-
-
-
-
-
12
13
14
15
10
11
12
13
14
15
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
-
-
-
-
-
-
-
-
HSI6A_CDRRSTb
FIFO7A_STRDb
FIFO6A_STRDb
HSI7A_CDRRST
SS_CLKOUT0N
SS_CLKOUT0P
SERDES Mode
HSI7A_SOUTN
HSI6A_SOUTN
HSI7_CSLOCK
HSI7A_SOUTP
HSI6A_SOUTP
HSI6_CSLOCK
HSI7A_SYDT
HSI6A_SYDT
SS_CLKIN0N
SS_CLKIN0P
HSI7A_SINN
HSI6A_SINN
HSI7A_SINP
HSI6A_SINP
I/O Pin
Note 4
Note 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
65
5
5
6
6
HSI5B_RXD0/TXD0
HSI7A_RXD9/TXD9
HSI7A_RXD8/TXD8
HSI7A_RXD7/TXD7
HSI7A_RXD6/TXD6
HSI7A_RXD5/TXD5
HSI7A_RXD4/TXD4
HSI7A_RXD3/TXD3
HSI7A_RXD2/TXD2
HSI7A_RXD1/TXD1
HSI7A_RXD0/TXD0
HSI6A_RXD9/TXD9
HSI6A_RXD8/TXD8
HSI6A_RXD7/TXD7
HSI6A_RXD6/TXD6
HSI6A_RXD5/TXD5
HSI6A_RXD4/TXD4
HSI6A_RXD3/TXD3
HSI6A_RXD2/TXD2
HSI6A_RXD1/TXD1
HSI6A_RXD0/TXD0
HSI7A_RECCLK
SERDES Mode
HSI6_RECCLK
HSI5B_SYDT
HSI7A_SYDT
HSI6A_SYDT
I/O Cell
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
5
5
5
ispGDX2 Family Data Sheet
FIFO5B_DIN0/DOUT0
FIFO7A_DIN9/DOUT9
FIFO7A_DIN8/DOUT8
FIFO7A_DIN7/DOUT7
FIFO7A_DIN6/DOUT6
FIFO7A_DIN5/DOUT5
FIFO7A_DIN4/DOUT4
FIFO7A_DIN3/DOUT3
FIFO7A_DIN2/DOUT2
FIFO7A_DIN1/DOUT1
FIFO7A_DIN0/DOUT0
FIFO6A_DIN9/DOUT9
FIFO6A_DIN8/DOUT8
FIFO6A_DIN7/DOUT7
FIFO6A_DIN6/DOUT6
FIFO6A_DIN5/DOUT5
FIFO6A_DIN4/DOUT4
FIFO6A_DIN3/DOUT3
FIFO6A_DIN2/DOUT2
FIFO6A_DIN1/DOUT1
FIFO6A_DIN0/DOUT0
FIFO7A_FIFORSTb
FIFO6A_FIFORSTb
FIFO7A_EMPTY
FIFO6A_EMPTY
FIFO Mode I/O
FIFO7A_ FULL
FIFO6A_ FULL
FIFO5B_FULL
Cell/Pin
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
fpBGA
GND
GND
GND
GND
484
W1
W2
W3
M5
M6
N7
K3
K2
N1
N6
N5
P6
P5
N3
N2
P3
P1
P7
R3
R2
R1
T2
U1
U2
R5
T6
U4
V4
V3
V2
R6
R7
V1
J4
J3
L6
L5
L4
T1
T3