LX128V-32FN208C Lattice, LX128V-32FN208C Datasheet - Page 61

• Manufacturer Part Number: LX128V-32FN208C
• Description: Analog & Digital Crosspoint ICs 128 I/O Switch Matrix, 3.3V, SERDES, 3.2ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX128V-32FN208C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispGDX2-128 Logic Signal Connections (Continued)
BK4_IO8
BK4_IO9 / PLL_FB0
BK4_IO10
BK4_IO11
GND
BK4_IO12
BK4_IO13
BK4_IO14
BK4_IO15 / VREF4
GOE1
TMS
GND
BK5_IO0 / VREF5
BK5_IO1
BK5_IO2
BK5_IO3
BK5_IO4
BK5_IO5
BK5_IO6
BK5_IO7
BK5_IO8
BK5_IO9
BK5_IO10
BK5_IO11
GND
BK5_IO12
BK5_IO13
BK5_IO14
BK5_IO15 / CLK_OUT0
GCLK/CE0
SEL0
SEL1
GCLK/CE1
BK6_IO0
BK6_IO1
BK6_IO2
BK6_IO3
GND
BK6_IO4
BK6_IO5
BK6_IO6
BK6_IO7
BK6_IO8
BK6_IO9
BK6_IO10
BK6_IO11
Signal Name
sysIO
Bank
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
-
-
Pair/Polarity
CLK0P
CLK0N
LVDS
36N
37N
38N
39N
40N
41N
42N
43N
44N
45N
46N
47N
48N
49N
50N
51N
52N
53N
36P
37P
38P
39P
40P
41P
42P
43P
44P
45P
46P
47P
48P
49P
50P
51P
52P
53P
Block MRB
GDX
2A
2A
2A
2A
2A
2A
2A
2A
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
2B
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
3A
-
-
-
-
-
-
-
-
10
11
12
13
14
15
10
11
12
13
14
15
10
11
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
-
-
-
-
-
-
-
-
-
-
HSI2B_CDRRSTb
HSI3A_CDRRSTb
FIFO2A_STRDb
FIFO2B_STRDb
FIFO3A_STRDb
SS_CLKOUT0N
SS_CLKOUT0P
SERDES Mode
HSI2A_SOUTN
HSI2A_SOUTP
HSI2B_SOUTP
HSI2B_SOUTN
HSI2_CSLOCK
HSI3_CSLOCK
HSI3A_SOUTN
HSI3A_SOUTP
HSI2B_SYDT
HSI3A_SYDT
SS_CLKIN0P
SS_CLKIN0N
HSI2B_SINP
HSI2B_SINN
HSI3A_SINN
HSI3A_SINP
58
I/O Pin
Note 4
Note 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
5
5
6
6
6
HSI2A_RXD7/TXD7
HSI2A_RXD6/TXD6
HSI2A_RXD5/TXD5
HSI2A_RXD4/TXD4
HSI2A_RXD3/TXD3
HSI2A_RXD2/TXD2
HSI2A_RXD1/TXD1
HSI2A_RXD0/TXD0
HSI2B_RXD9/TXD9
HSI2B_RXD8/TXD8
HSI2B_RXD7/TXD7
HSI2B_RXD6/TXD6
HSI2B_RXD5/TXD5
HSI2B_RXD4/TXD4
HSI2B_RXD3/TXD3
HSI2B_RXD2/TXD2
HSI2B_RXD1/TXD1
HSI2B_RXD0/TXD0
HSI3A_RXD9/TXD9
HSI3A_RXD8/TXD8
HSI3A_RXD7/TXD7
HSI3A_RXD6/TXD6
HSI3A_RXD5/TXD5
HSI3A_RXD4/TXD4
HSI3A_RXD3/TXD3
HSI2B_RECCLK
HSI3A_RECCLK
SERDES Mode
HSI2B_SYDT
I/O Cell
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ispGDX2 Family Data Sheet
2
5
FIFO2A_DIN7/DOUT7
FIFO2A_DIN6/DOUT6
FIFO2A_DIN5/DOUT5
FIFO2A_DIN4/DOUT4
FIFO2A_DIN3/DOUT3
FIFO2A_DIN2/DOUT2
FIFO2A_DIN1/DOUT1
FIFO2A_DIN0/DOUT0
FIFO2B_DIN9/DOUT9
FIFO2B_DIN8/DOUT8
FIFO2B_DIN7/DOUT7
FIFO2B_DIN6/DOUT6
FIFO2B_DIN5/DOUT5
FIFO2B_DIN4/DOUT4
FIFO2B_DIN3/DOUT3
FIFO2B_DIN2/DOUT2
FIFO2B_DIN1/DOUT1
FIFO2B_DIN0/DOUT0
FIFO3A_DIN9/DOUT9
FIFO3A_DIN8/DOUT8
FIFO3A_DIN7/DOUT7
FIFO3A_DIN6/DOUT6
FIFO3A_DIN5/DOUT5
FIFO3A_DIN4/DOUT4
FIFO3A_DIN3/DOUT3
FIFO2B_FIFORSTb
FIFO3A_FIFORSTb
FIFO2B_EMPTY
FIFO3A_EMPTY
FIFO Mode I/O
FIFO2B_FULL
Cell/Pin
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
fpBGA
GND
GND
GND
GND
208
M2
M4
M3
A3
C5
D5
B4
A2
B3
C4
R1
D3
C2
D2
E3
E4
E2
C1
G3
G4
D1
G2
H4
H3
D9
G1
D8
K3
N1
A4
A8
B1
F3
F2
F1
K1
K2
K4
L1
L2
J4
J3