LAN83C185-JD SMSC, LAN83C185-JD Datasheet - Page 19

• Manufacturer Part Number: LAN83C185-JD
• Description: Ethernet ICs Lo Pwr 10/100 3.3V PHY
• Manufacturer: SMSC

Specifications of LAN83C185-JD

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-TX, 10BASE-T
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 1 mA, 19 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
4.3
4.3.1
4.3.2
4.3.3
MAC
Converter
Converter
NRZI
100Base-TX Receive
A/D
The receive data path is shown in
100M Receive Input
The MLT-3 from the cable is fed into the PHY (on inputs RXP and RXN) via a 1:1 ratio transformer.
The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64-
level quanitizer it generates 6 digital bits to represent each sample. The DSP adjusts the gain of the
ADC according to the observed signal levels such that the full dynamic range of the ADC can be used.
Equalizer, Baseline Wander Correction and Clock and Data Recovery
The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates
for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors,
and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m
and 150m.
If the DC content of the signal is such that the low-frequency components fall below the low frequency
pole of the isolation transformer, then the droop characteristics of the transformer will become
significant and Baseline Wander (BLW) on the received signal will result. To prevent corruption of the
received data, the PHY corrects for BLW and can receive the ANSI X3.263-1995 FDDI TP-PMD
defined “killer packet” with no bit errors.
The 100M PLL generates multiple phases of the 125MHz clock. A multiplexer, controlled by the timing
unit of the DSP, selects the optimum phase for sampling the data. This is used as the received
recovered clock. This clock is used to extract the serial data from the received signal.
NRZI and MLT-3 Decoding
The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then
converted to an NRZI data stream.
MII 25MHz by 4
RX_CLK
NRZI
bits
MLT-3
Converter
MLT-3
Magnetics
100M
PLL
MII
Figure 4.2 Receive Data Path
MLT-3
DATASHEET
Figure
125 Mbps Serial
MLT-3
by 4 bits
25MHz
4.2. Detailed descriptions are given below.
6 bit Data
19
RJ45
Decoder
4B/5B
and BLW Correction
recovery, Equalizer
MLT-3
DSP: Timing
25MHz by
CAT-5
5 bits
Descrambler
and SIPO
Revision 0.8 (06-12-08)