AT84CS001VTPY E2V, AT84CS001VTPY Datasheet - Page 25

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AT84CS001VTPY

Manufacturer Part Number
AT84CS001VTPY
Description
Demultiplexer 240-Pin EBGA
Manufacturer
E2V
Datasheet

Specifications of AT84CS001VTPY

Package
240EBGA
Power Supply Type
Analog|Digital
Typical Supply Current
600 mA
Typical Operating Supply Voltage
3.3 V
Minimum Operating Supply Voltage
2.375|3.15 V
Maximum Operating Supply Voltage
2.625|3.45 V
Table 5-1.
e2v semiconductors SAS 2009
Symbol
B0, B1, B2, B3, B4, B5, B6, B7,
B8, B9
B0N, B1N, B2N, B3N, B4N,
B5N, B6N, B7N, B8N, B9N
BOR/DRBN
BORN/DRB
C0, C1, C2, C3, C4, C5, C6,
C7, C8, C9
C0N, C1N, C2N, C3N, C4N,
C5N, C6N, C7N, C8N, C9N
COR/DRCN
CORN/DRC
D0, D1, D2, D3, D4, D5, D6,
D7, D8, D9
D0N, D1N, D2N, D3N, D4N,
D5N, D6N, D7N, D8N, D9N
DOR/DRDN
DORN/DRD
DR
DRN
DAO
DAON
Additional Functions
ASYNCRST
CLKTYPE
DRTYPE
CLKDACTRL
DACTRL
DAEN
RS
SLEEP
Pin Description (Continued)
Pin Number
B5, B4, B3, B2, C2, D2, E2, F2,
G2, H2
A5, A4, A3, A2, B1, C1, D1, E1,
F1, G1
J2
H1
M2, N2, P2, R2, T2, U2, V1, V2,
V3, V4
L1, M1, N1, P1, R1, T1, U1,
W2, W3, W4
V5
W5
V6, V7, V8, V9, V10, V11, V12,
V13, V14, V15
W6, W7, W8, W9, W10, W11,
W12, W13, W14, W15
V16
W16
J1
K2
R18
R19
B17
V18
K1
V19
W18
W17
L2
A18
Function
In-phase (+) digital outputs for port B
B0 is the LSB, B9 is the MSB
Inverted phase (-) digital outputs for port B
In-phase (+) additional bit output for port B or inverted phase
(-) output clock in staggered mode for port B
Inverted phase (-) additional bit output for port B or in-phase (+)
output clock in staggered mode for port B
In-phase (+) digital outputs for port C
C0 is the LSB, C9 is the MSB
Inverted phase (-) digital outputs for port C
In-phase (+) additional bit output for port C or inverted phase
(-) output clock in staggered mode for port C
Inverted phase (-) additional bit output for port C or in-phase (+)
output clock in staggered mode for port C
In-phase (+) digital outputs for port D
D0 is the LSB, D9 is the MSB
Inverted phase (-) digital outputs for port D
In-phase (+) additional bit output for port D or inverted phase
(-) output clock in staggered mode for port D
Inverted phase (-) additional bit output for port D or in-phase (+)
output clock in staggered mode for port D
In-phase (+) data ready signal output
Inverted phase (-) data ready signal output
In-phase (+) output signal for standalone delay cell
Inverted phase (-) output signal for standalone delay cell
Asynchronous reset signal
Input clock type selection signal
Output clock type selection signal
Clock delay cell control signal
Standalone delay cell control signal
Standalone delay cell enable signal
Ratio selection signal
Sleep mode enable
0809E–BDC–05/09
AT84CS001
25

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