AT84CS001VTPY E2V, AT84CS001VTPY Datasheet - Page 8

• Manufacturer Part Number: AT84CS001VTPY
• Description: Demultiplexer 240-Pin EBGA
• Manufacturer: E2V

Specifications of AT84CS001VTPY

• Package: 240EBGA
• Power Supply Type: Analog|Digital
• Typical Supply Current: 600 mA
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 2.375|3.15 V
• Maximum Operating Supply Voltage: 2.625|3.45 V

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0809E–BDC–05/09
For correct logic 1 or 0 settings, please refer to
When CLKTYPE is left floating, the default (recommended) mode is selected (CLK/2).
Notes:
Figure 3-5.
Figure 3-6.
Note:
Table 3-4.
Table 3-5.
• When CLKTYPE is at logic 0 and DRTYPE is at logic 1, the DMUX is set to CLK and DR modes for
• When CLKTYPE is at logic 1 and DRTYPE is at logic 0, the CLK/2 and DR/2 modes are activated for
both the input and output clocks – only the rising edges of the input and output clocks are active and
the input and output clock rates are the same as the input and output data rate.
both the input and output clocks, both the rising and falling edges of the input and output clocks are
active and the input and output clock rates are half the input and output data rate.
1. CLK or CLK/2 and DR or DR/2 modes can be indifferently combined together
2. The preferred (and recommended) mode is CLK/2 together with DR/2.
In
ratio, the DR and data-out frequencies are equal to one quarter of the CLK and data-in frequencies.
Figure 3-5
(example: CLK/2 for the input and DR for the output).
(CLK,CLKN)
or (DR,DRN)
(CLK,.CLKN)
or (DR,DRN)
CLK and DR Mode (CLKTYPE = 0, DRTYPE = 1)
CLK/2 and DR/2 Mode (CLKTYPE = 1, DRTYPE = 0)
Logical Settings of the DMUX Input Clock Type Selection
Logical Settings of the DMUX Output Clock Type Selection
Data In or
Data In or
Data Out
Data Out
CLKTYPE
DRTYPE
and
0
1
1
0
Figure 3-6
above, the CLK and DR signals are not on the same time scale. In 1:4 DMUX
“Control Signal Settings” on page
DMUX Output Clock Type
DMUX Input Clock Type
CLK/2
DR/2
CLK
DR
e2v semiconductors SAS 2009
5.
AT84CS001