LAN9303-ABZJ Standard Microsystem (Smsc), LAN9303-ABZJ Datasheet - Page 50
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LAN9303-ABZJ
Manufacturer Part Number
LAN9303-ABZJ
Description
Ethernet Switch 3-Port 10Mbps/100Mbps 56-Pin QFN EP
Manufacturer
Standard Microsystem (Smsc)
Datasheet
1.LAN9303-ABZJ.pdf
(367 pages)
Specifications of LAN9303-ABZJ
Package
56QFN EP
Phy/transceiver Interface
MII/RMII
Number Of Primary Switch Ports
3
Maximum Data Rate
100 Mbps
Vlan Support
Yes
Power Supply Type
Analog
Minimum Single Supply Voltage
3 V
Maximum Single Supply Voltage
3.6 V
Maximum Supply Current
0.19(Typ) A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LAN9303-ABZJ
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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Revision 1.4 (07-07-10)
STRAP NAME
speed_strap_2
duplex_strap_2
BP_EN_strap_2
FD_FC_strap_2
Table 4.2 Soft-Strap Configuration Strap Definitions (continued)
DESCRIPTION
Port 2 Speed Select Strap: This strap affects the default
value of the following register bits (x=2):
Refer to the respective register definition sections for
additional information.
Port 2 Duplex Select Strap: This strap affects the default
value of the following register bits (x=2):
Refer to the respective register definition sections for
additional information.
Port 2 Backpressure Enable Strap: Configures the
default value for the
(BP_EN_2)
(MANUAL_FC_2).
Port 2 Full-Duplex Flow Control Enable Strap: This strap
is used to configure the default value of the following
register bits:
This strap may affect the default value of the following
register bits (x=2):
Refer to the respective register definition sections for
additional information.
Speed Select LSB (PHY_SPEED_SEL_LSB)
Port x PHY Basic Control Register
(PHY_BASIC_CONTROL_x)
10BASE-T Full Duplex
of the
Register (PHY_AN_ADV_x)
PHY Mode (MODE[2:0])
Modes Register (PHY_SPECIAL_MODES_x)
Duplex Mode (PHY_DUPLEX)
Control Register (PHY_BASIC_CONTROL_x)
10BASE-T Full Duplex
Negotiation Advertisement Register (PHY_AN_ADV_x)
PHY Mode (MODE[2:0])
Modes Register (PHY_SPECIAL_MODES_x)
Port 2 Full-Duplex Transmit Flow Control Enable
(TX_FC_2)
Enable (RX_FC_2)
Register (MANUAL_FC_2)
Asymmetric Pause
Advertisement Register (PHY_AN_ADV_x)
Port x PHY Auto-Negotiation Advertisement
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
bit of the
and
DATASHEET
Port 2 Full-Duplex Receive Flow Control
Port 2 Backpressure Enable
bit of the
bits of the
Port 2 Manual Flow Control Register
50
bit and
bit of the
bits of the
bits of the
.
Port x PHY Auto-Negotiation
Port 2 Manual Flow Control
bit of the
10BASE-T Half Duplex
Port x PHY Auto-
Port x PHY Special
Port x PHY Special
Port x PHY Basic
bit of the
bit
SMSC LAN9303/LAN9303i
PIN / DEFAULT
VALUE
1b
1b
1b
1b
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