LAN9303-ABZJ Standard Microsystem (Smsc), LAN9303-ABZJ Datasheet - Page 66
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LAN9303-ABZJ
Manufacturer Part Number
LAN9303-ABZJ
Description
Ethernet Switch 3-Port 10Mbps/100Mbps 56-Pin QFN EP
Manufacturer
Standard Microsystem (Smsc)
Datasheet
1.LAN9303-ABZJ.pdf
(367 pages)
Specifications of LAN9303-ABZJ
Package
56QFN EP
Phy/transceiver Interface
MII/RMII
Number Of Primary Switch Ports
3
Maximum Data Rate
100 Mbps
Vlan Support
Yes
Power Supply Type
Analog
Minimum Single Supply Voltage
3 V
Maximum Single Supply Voltage
3.6 V
Maximum Supply Current
0.19(Typ) A
Available stocks
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Part Number:
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20 000
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Revision 1.4 (07-07-10)
6.3.2
6.3.2.1
Transmit MAC
The transmit MAC generates an Ethernet MAC frame from TX FIFO data. This includes generating the
preamble and SFD, calculating and appending the frame checksum value, optionally padding
undersize packets to meet the minimum packet requirement size (64 bytes), and maintaining a
standard inter-frame gap time during transmit.
The transmit MAC can operate at 10/100Mbps, half- or full-duplex, and with or without flow control
depending on the state of the transmission. In half-duplex mode, the transmit MAC meets CSMA/CD
IEEE 802.3 requirements. The transmit MAC will re-transmit if collisions occur during the first 64 bytes
(normal collisions), or will discard the packet if collisions occur after the first 64 bytes (late collisions).
The transmit MAC follows the standard truncated binary exponential back-off algorithm, collision and
jamming procedures.
The transmit MAC pre-pends the standard preamble and SFD to every packet from the FIFO. The
transmit MAC also follows, as default, the standard Inter-Frame Gap (IFG). The default IFG is 96 bit
times and can be adjusted via the IFG Config field of the
(MAC_TX_CFG_x).
Packet padding and cyclic redundant code (FCS) calculation may be optionally performed by the
transmit MAC. The auto-padding process automatically adds enough zeros to packets shorter than 64
bytes. The auto-padding and FCS generation is controlled via the
Transmit Configuration Register
The transmit FIFO acts as a temporary buffer between the transmit MAC and the Switch Engine. The
FIFO logic manages the re-transmission for normal collision conditions or discards the frames for late
or excessive collisions.
When in full-duplex mode, the transmit MAC uses the flow-control algorithm specified in IEEE 802.3.
MAC pause frames are used primarily for flow control packets, which pass signalling information
between stations. MAC pause frames have a unique type of 8808h, and a pause op-code of 0001h.
The MAC pause frame contains the pause value in the data field. The flow control manager will auto-
adapt the procedure based on traffic volume and speed to avoid packet loss and unnecessary pause
periods.
When in half-duplex mode, the MAC uses a back pressure algorithm. The back pressure algorithm is
based on a forced collision and an aggressive back-off algorithm.
Transmit Counters
The transmit MAC gathers statistics on each packet and increments the related counter registers. The
following transmit counters are supported for each Switch Fabric port. Refer to
Accessible Switch Control and Status Registers,” on page 212
Section 13.4.2.42
Total packets deferred
Total pause packets
Total OK packets
Total packets 64 bytes in size
Total packets 65 through 127 bytes in size
Total packets 128 through 255 bytes in size
Total packets 256 through 511 bytes in size
Total packets 512 through 1023 bytes in size
Total packets 1024 through maximum bytes in size
Total undersized packets
Total bytes transmitted from all packets
Total broadcast packets
for detailed descriptions of these counters.
(Section 13.4.2.27, on page
(Section 13.4.2.26, on page
(Section 13.4.2.25, on page
(Section 13.4.2.36, on page
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
(Section 13.4.2.34, on page
(MAC_TX_CFG_x).
(Section 13.4.2.28, on page
DATASHEET
66
(Section 13.4.2.35, on page
(Section 13.4.2.29, on page
(Section 13.4.2.31, on page
(Section 13.4.2.30, on page
(Section 13.4.2.32, on page
253)
252)
251)
(Section 13.4.2.33, on page
262)
Port x MAC Transmit Configuration Register
260)
254)
TX Pad Enable
and
261)
Section 13.4.2.25
255)
257)
256)
SMSC LAN9303/LAN9303i
258)
Table 13.14, “Indirectly
bit of the
259)
Port x MAC
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