MT48H4M32LFB5-75 IT:K Micron Technology Inc, MT48H4M32LFB5-75 IT:K Datasheet - Page 22
MT48H4M32LFB5-75 IT:K
Manufacturer Part Number
MT48H4M32LFB5-75 IT:K
Description
DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 1.8V 90-Pin VFBGA Tray
Manufacturer
Micron Technology Inc
Type
Mobile SDRAMr
Datasheet
1.MT48H8M16LFB4-6K.pdf
(86 pages)
Specifications of MT48H4M32LFB5-75 IT:K
Package
90VFBGA
Density
128 Mb
Address Bus Width
14 Bit
Operating Supply Voltage
1.8 V
Maximum Clock Rate
133 MHz
Maximum Random Access Time
8|5.4 ns
Operating Temperature
-40 to 85 °C
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PDF: 09005aef832ff1ea
128mb_mobile_sdram_y35M.pdf - Rev. G 10/09 EN
10. For auto precharge mode, the precharge timing budget (
11. CLK must be toggled a minimum of two times during this period.
12. Required clocks are specified by JEDEC functionality and are not dependent on any tim-
13. Timing is specified by
14. Timing is specified by
15. Timing is specified by
16. Based on
9. AC characteristics assume
timing must be derated. Input setup times require an additional 50ps for each 100 mV/
ns reduction in slew rate. Input hold times remain unchanged. If the slew rate exceeds
4.5V/ns, functionality is uncertain.
after the first clock delay and after the last WRITE is executed.
ing parameter.
cycle rate.
t
CK (MIN), CL = 3.
Electrical Specifications – AC Operating Conditions
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
t
t
t
CKS. Clock(s) specified as a reference only at minimum cycle rate.
WR plus
WR.
22
t
T = 1ns. For command and address input slew rates <0.5V/ns,
t
RP. Clock(s) specified as a reference only at minimum
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RP) begins at
©2008 Micron Technology, Inc. All rights reserved.
t
RP – (1 ×
t
CKns),
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