MT48LC16M16A2P-6A:D Micron Technology Inc, MT48LC16M16A2P-6A:D Datasheet - Page 58

DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II Tray

MT48LC16M16A2P-6A:D

Manufacturer Part Number
MT48LC16M16A2P-6A:D
Description
DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II Tray
Manufacturer
Micron Technology Inc
Type
SDRAMr

Specifications of MT48LC16M16A2P-6A:D

Density
256 Mb
Maximum Clock Rate
167 MHz
Package
54TSOP-II
Address Bus Width
15 Bit
Operating Supply Voltage
3.3 V
Maximum Random Access Time
5.4 ns
Operating Temperature
0 to 70 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
256M (16Mx16)
Speed
167MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
54-TSOP II
Organization
16Mx16
Address Bus
15b
Access Time (max)
5.4ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
135mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT48LC16M16A2P-6A:D
Manufacturer:
MICRON/美光
Quantity:
20 000
Figure 27: Alternating Bank Read Accesses
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. N 1/10 EN
Command
BA0, BA1
Address
DQM
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
ACTIVE
Bank 0
T0
Row
Row
t CKH
t CMH
t AH
t AH
t AH
t RCD - bank 0
t RAS - bank 0
t RC - bank 0
t RRD
t CK
Note:
T1
NOP
1. For this example, BL = 4 and CL = 2.
Enable auto precharge
t CMS
t CL
Column m
Bank 0
T2
READ
t CMH
t CH
CL - bank 0
T3
NOP
t LZ
t AC
58
ACTIVE
Bank 3
T4
Row
Row
D
OUT
t OH
t AC
t RCD - bank 3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T5
D
NOP
OUT
t OH
t AC
Enable auto precharge
256Mb: x4, x8, x16 SDRAM
Column b
Bank 3
T6
READ
D
OUT
t OH
t AC
1
t RP - bank 0
CL - bank 3
© 1999 Micron Technology, Inc. All rights reserved.
T7
NOP
D
READ Operation
Don’t Care
OUT
t OH
t AC
Bank 0
Row
Row
T8
ACTIVE
D
OUT
t OH
t RCD - bank 0
Undefined
t AC

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